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This paper presents a comprehensive simulation analysis of the dynamic operation of T-RAM cells. The analysis addresses the evolution of cell electrostatics and of carrier concentrations and flows in the device when the gate voltage undergoes a fast low-to-high switch, as required by both read and write operations. The results clarify, first of all, the basic physics making holes in the p-base the physical element allowing information storage in the device. From this starting point, the working principles exploited for DRAM operation of the memory cell are then explained.

This paper presents an experimental investigation of the turn-ON of nanoscale T-RAM cells under the transient conditions given by the depletion of the $p$ -base from holes. Data reveal that hole depletion increases the dynamic turn-ON voltage of the device for a stretch of time depending on the gate and anode bias during the hold phase and on the gate voltage used for device sensing. The results are explained considering that the gate and anode biases during hold affect the rate of hole generation bringing the device back to its equilibrium condition, while the gate voltage applied to sense the state of the gated-thyristor determines the $p$ -base potential and, therefore, the amount of holes in the $p$ -base required to turn the device on.

This paper investigates the limitations to the accuracy and the main issues of the spectroscopic analyses of random telegraph noise (RTN) traps in nanoscale MOSFETs. First, the impact of the major variability sources affecting decananometer MOSFET performance on both the RTN time constants and the trap depth estimation is studied as a function of the gate overdrive. Results reveal that atomistic doping and metal gate granularity broaden the statistical distribution of the RTN time constants far more than what comes from the random position of the RTN trap in the 3-D device electrostatics, contributing, in turn, to a significant reduction of the accuracy of trap spectroscopy. The accuracy is shown to improve the higher is the gate overdrive, owing to a more uniform and gate-bias-independent surface potential in the channel, with, however, the possible drawback of triggering the simultaneous trap interaction with both the channel and the gate. This simultaneous interaction is, finally, shown to critically compromise trap spectroscopy in thin-oxide devices.

This paper presents a detailed simulation analysis of the impact of 3-D electrostatics and atomistic doping on the variability of the random telegraph noise (RTN) time constants in nanoscale MOS devices. Results on a template decananometer Flash cell show that both the effects contribute to a large statistical dispersion of the capture/emission time constants of oxide traps placed at the same distance from the silicon surface, mainly due to nonuniform channel inversion. The statistical dispersion has an orders-of-magnitude increase when moving from the on-state to the subthreshold cell regimes and has major implications on the spectroscopic investigation of RTN traps, as will be discussed in Part II of this work.

This letter discusses the working principles of a memory cell exploiting the bistability of a single nanoscale gated-thyristor to achieve high-performance DRAM operation (T-RAM cell). The device relies on the possibility to reach either of the two stable states of the thyristor by means of a fast low-to-high gate switch and depending on the amount of holes in the gated p-base. In particular, with proper selection of the low and high gate levels, the stationary hole concentration in the p-base leads the thyristor to its high current state while hole depletion results in an orders-of-magnitude lower anode current. This opens the possibility for a DRAM technology with a simple back-end process and fast WRITE and READ operations with low voltage requirements.

Demand for on chip memories has increased due to the need for more data storage and the increasing gap between processor and off chip memory speed. One of the solutions proposed to improve power consumption and to fill the memory gap is to introduce non volatility at different levels of the memory hierarchy (storage class, main memory, cache memory). Several disruptive technologies have been proposed in the last decades for non-volatile memory (NVM) applications. The more investigated ones are Phase-Change Memories (PCM), Conducting-Bridge RAM (CBRAM), Oxide-based Resistive RAM (OxRAM), and Perpendicular Spin Transfer Torque Magnetic Memories (pSTTMRAM). Intensive studies and demonstrations have being carried out in order to develop and improve those emerging memory concepts. Some memory stacks have shown promising results in term of high speed, good endurance or retention but not necessarily all of the above. A survey of published results [1] as well as internal studies carried out at LETI [2, 3] using a memory test vehicle developed to evaluate various memory concepts using the same 130nm CMOS logic have led us to infirm that the universal memory ie an optimized memory stack that fits all requests of memory hierarchy does not exist. However, because requirements for cache memories (ie high speed, endurance, but low data retention) are completely different from requirements for embedded memories (ie high temperature or long data retention), different technology or optimized memory stacks can be targeted to fulfill specific applications. It will be shown that despite very different physical concepts, universal signatures can be extracted unifying the characteristics of different technologies and thus drawing conclusions on their behaviors and tradeoffs (such as programming window vs endurance, programming window vs data retention, and endurance vs data retention). This is illustrated in Fig 1 where the relation between the programming window and the endurance capabilities of the different technologies is presented. It is shown that high programming window is typically associated to poor endurance capabilities, (as shown by some classes of chalco-based CBRAM or non-polar OxRAM). For these technologies the overall filament is believed to participate to the creation and the dissolution events. On the contrary, displacing very few atoms/ions, or spins, during the write or erase event allows to guarantee a long-lasting endurance (examples are certain class of polar OxRAM and STT MRAMs). Data also show that a universal tradeoff exists between the endurance and data retention itself. The better the performances in endurance, the lower the data retention capabilities at high temperature. Write latency speed will be discussed and ultra fast ( The characteristics and performances of the different emerging will be presented (materials, integration, speed, endurance, consumption and scalability) in regards of the needed specifications required for potential applications. [1] ] H.-S. P. Wong, C. Ahn, J. Cao, et al., “Stanford Memory Trends,” https://nano.stanford.edu/stanford-memory-trends, accessed Nov 11, 2015 [2] C. Nail; G. Molas; P. Blaise et al “ Understanding RRAM endurance, retention and window margin trade-off using experimental results and simulations”: IEDM 2016 Pages: 4.5.1 - 4.5.4, DOI: 10.1109/IEDM.2016.7838346 [3] V. Sousa, G. Navarro, N. Castellani et al., “Operation Fundamentals in 12Mb Phase Change Memory Based on Innovative Ge-rich GST Materials Featuring High Reliability Performance”, VLSI Tech. Symp., pp.98-99, 2015 Figure 1

International audience; Sb-rich GeSbTe based Phase-Change Memories (PCM) were studied in the last years for their high switching speed to target Storage Class Memory (SCM) applications. In this work, we show the advantages of an engineered Multilayered Sb-rich GeSbTe stack compared to standard bulk reference materials. The studied Multilayer-based PCM devices feature a lower programming current with respect to the equivalent bulk ones, preserving a high programming speed. Furthermore, Multilayered Sb-rich GeSbTe brings better endurance performances for a wide programming current range and extremely reduced cycle-to-cycle (C2C) and device-to-device (D2D) variability along cycling verified in 4 kb PCM arrays. These results confirm the improved yield and reliability obtained thanks to Multilayered PCM solution.