26 results on '"Mitard, Jerome"'
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2. Automatic Prediction of Metal–Oxide–Semiconductor Field‐Effect Transistor Threshold Voltage Using Machine Learning Algorithm
3. Automatic Prediction of Metal–Oxide–Semiconductor Field‐Effect Transistor Threshold Voltage Using Machine Learning Algorithm
4. NH3 PDA Temperature-Impact on Low-Frequency Noise Behavior of Si0.7Ge0.3 pFinFETs
5. 3-D Full-Band Monte Carlo Simulation of Hot-Electron Energy Distributions in Gate-All-Around Si Nanowire MOSFETs
6. NH3 PDA Temperature-Impact on Low-Frequency Noise Behavior of Si0.7Ge0.3 pFinFETs
7. Understanding and optimization of hot-carrier reliability in germanium-on-silicon pMOSFETs
8. Carrier transport in HfO2/metal gate MOSFETs: Physical insight into critical parameters
9. Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle
10. Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling
11. Vₜ Extraction Methodologies Influence Process Induced Vₜ Variability: Does This Fact Still Hold for Advanced Technology Nodes?
12. Comparison of Temperature Dependent Carrier Transport in FinFET and Gate-All-Around Nanowire FET
13. Ge Devices: A Potential Candidate for Sub-5-nm Nodes?
14. Gate Metal and Cap Layer Effects on Ge nMOSFETs Low-Frequency Noise Behavior
15. Analog Performance and its Variability in Sub-10 nm Fin-Width FinFETs: a Detailed Analysis
16. On The Development of a Reliable Gate Stack for Future Technology Nodes Based on III-V Materials
17. A Comparative Study of Defect Energy Distribution and Its Impact on Degradation Kinetics in GeO2/Ge and SiON/Si pMOSFETs
18. Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes
19. Diffusion and Gate Replacement: A New Gate-First High- $k$ /Metal Gate CMOS Integration Scheme Suppressing Gate Height Asymmetry
20. Low-Frequency Noise Characterization of GeOx Passivated Germanium MOSFETs
21. High-Performance Si0.45Ge0.55Implant-Free Quantum Well pFET With Enhanced Mobility by Low-Temperature Process and Transverse Strain Relaxation
22. Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes.
23. Theory and Experiments of the Impact of Work-Function Variability on Threshold Voltage Variability in MOS Devices
24. Interface and Border Traps in Ge pMOSFETs
25. High-Performance Si0.45Ge0.55 Implant-Free Quantum Well pFET With Enhanced Mobility by Low-Temperature Process and Transverse Strain Relaxation.
26. Characterization of Negative-Bias Temperature Instability of Ge MOSFETs With GeO2/Al2O3 Stack.
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