1. IBM z14: Enabling physical design in 14-nm technology for high-performance, high-reliability microprocessors
- Author
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S. Tsapepas, T. Schell, A. Bianchi, Michael S. Gray, Jeffrey A. Zitz, Erwin Behnen, R. Serton, James D. Warnock, Matthew T. Guzowski, L. Darden, D. Bradley, W. Ansley, Nagu Dhanwada, Robert M. Averill, Gustavo E. Tellez, Christopher J. Berry, L. Sigal, John D. Davis, Y.H. Chan, K. Acharya, M. DeHond, Michael R. Scheuermann, Hunter Shi, Tobias Werner, David H. Wolpert, D. Phan, G. Wiedemeier, K. G. Barkley Iii, Michael H. Wood, Sungjae Lee, and R. Veerabhadraiah more...
- Subjects
010302 applied physics ,Standard cell ,General Computer Science ,Computer science ,business.industry ,020208 electrical & electronic engineering ,02 engineering and technology ,01 natural sciences ,Automation ,Reliability (semiconductor) ,Computer architecture ,0103 physical sciences ,0202 electrical engineering, electronic engineering, information engineering ,Multiple patterning ,Node (circuits) ,Routing (electronic design automation) ,IBM ,Physical design ,business - Abstract
The IBM z14 design was built with the 14-nm high-performance silicon-on-insulator (SOI) technology of GLOBALFOUNDRIES. This was the first technology node after IBM transitioned from its integrated fabrication facility to operating in a fabless environment, driving significant changes to design processes and methodology. In addition to this partnership, the 14-nm technology introduced significant changes relative to previous technology nodes, including the introduction of fin-shaped field-effect transistors, the use of double patterning for the lowest back-end-of-line layers, and the introduction of middle-of-line layers to exploit contact layers for local interconnects. This combination of technical and business challenges required numerous large-scale innovations for our design, design team, and design methodologies. In this paper, we provide a survey of these innovations, including the fin-based standard cell image, deeply scaled SOI self-heating/electromigration verification, routing strategies to handle double-patterning with interlayer via awareness, fill automation to enable simultaneous design of multiple layers of hierarchy, and high-performance array design with the voltage and noise limitations of the 14-nm technology node. more...
- Published
- 2018
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