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A high accuracy and high sensitivity system architecture is proposed for the read-out circuit of electrical impedance tomography system-on-chip. The switched ratiometric technique is applied in the proposed architecture. The proposed system architecture minimizes the device noise by processing signals from both read-out electrodes and the stimulus. The quantized signals are post-processed in the digital processing unit for proper signal demodulation and impedance ratio calculation. Our proposed architecture improves the sensitivity of the read-out circuit, cancels out the gain fluctuations in the system, and overcomes the effects of motion artifacts on measurements.

At advanced process nodes, lithography weakpoints can exist in physical layouts of integrated circuit designs even if the layouts pass design rule checking (DRC). Existence of lithography weakpoints in a physical layout can cause manufacturability issues, which in turn can result in yield losses. In our experiments, we have found that specific standard cells have tendencies to create lithography weakpoints after their cell instances are placed and routed, even though each of these cells does not contain any lithography weakpoint before performing placement and routing. In addition, our experiments have shown that abutted standard cell instances can induce lithography weakpoints. Therefore, in this paper, we propose methodologies that are used in a novel software system for checking standard cells in terms of the aforementioned lithography issues. Specifically, the software system is capable of detecting and sorting problematic standard cells which are prone to generate lithography weakpoints, as well as reporting standard cells that should not be abutted. Methodologies proposed in this paper allow us to reduce or even prevent the generation of undesirable lithography weakpoints during the physical synthesis phase of designing a digital integrated circuit.

Vehicle-to-vehicle communications can change the driving behavior of drivers significantly by providing them rich information on downstream traffic flow conditions. This study seeks to model the varying car-following behaviors involving connected vehicles and human-driving vehicles in mixed traffic flow. A revised car-following model is developed using an intelligent driver model (IDM) to capture drivers' perceptions of their preceding traffic conditions through vehicle-to-vehicle communications. Stability analysis of the mixed traffic flow is conducted for a specific case. Numerical results show that the stable region is apparently enlarged compared with the IDM., Comment: Presented at the 8th Annual IEEE Int. Conf. on CYBER Technology in Automation, Control, and Intelligent Systems

At advanced process nodes, pattern matching techniques have been used in the detection of lithography hotspots, which can affect yields of manufactured integrated circuits. Although commercial pattern matching and in-design hotspot fixing tools have been developed, engineers still need to verify that specific hotspot patterns in routed designs can indeed be detected or even repaired by software tools. Therefore, there is the need to create test cases with which targeted hotspot patterns can be generated in routed layouts by using an APR (automatic placement and routing) tool. In this paper, we propose a methodology of creating hotspot patterns in the routing space by using Synopsys tools. Also, methods for repairing hotspots during the physical design phase are presented. With the use of the proposed hotspot creation methodology, we can generate routed designs containing targeted hotspot patterns. As a result, the effectiveness of hotspot detection rules, hotspot fixing guidance rules, and relevant software tool functions can be verified.

To evaluate the quality of physical layout designs in terms of manufacturability, DFM rule scoring techniques have been widely used in physical design and physical verification phases. However, one major drawback of conventional DFM rule scoring methodologies is that resultant DFM rule scores may not accurate since the scores may not highly correspond to lithography simulation results. For instance, conventional DFM rule scoring methodologies usually use rule-based techniques to compute scores without considering neighboring geometric scenarios of targeted layout shapes. That can lead to inaccurate scoring results since computed DFM rule scores can be either too optimistic or too pessimistic. Therefore, in this paper, we propose a novel approach with the use of machine learning technology to analyze the context of targeted layouts and predict their lithography impacts on manufacturability.

While standard cell layouts are drawn with minimum design rules to maximize the benefit of design area shrinkage, the complicated design rules have caused difficulties with signal routes accessing the pins in standard cell layouts. As a result, it has become a great challenge for physical layout designers to design a standard cell layout that is optimized for area, power, timing, signal integrity, and printability. Multiple design iterations are required to consider pin accessibility during standard cells layout to increase the number of feasible solutions available to the router. In this work, we will demonstrate several improvements with the Synopsys PAC methodology, such as reducing the number of cells required for each Synopsys 'testcell' with the same cell abutment condition, increasing the complexity of the pin connection for better pin accessibility evaluation. We also recommend additional constraints to improve the probability of detecting pin accessibility issues. We also integrate other physical verification methods to access the design rule compliance and the printability of standard cells. We hope that the easy to use utility enables layout engineers to perform the verification, simplifying the verification methodology., Comment: Synopsys User Group Singapore (SNUG) 2017. arXiv admin note: substantial text overlap with arXiv:1805.10012, arXiv:1805.10745

Starting from 22-nm, a standard cell must be designed to be full lithography-compliant, which includes Design Rule Check, Design-for-Manufacturability and Double-Patterning compliant. It has become a great challenge for physical layout designers to provide a full lithography-compliant standard cell layout that is optimized for area, power, timing, signal integrity, and yield. This challenge is further exacerbated with abutted single- and multiple-height standard cells. At present, different foundries and library vendors have different approaches for full lithography-compliant library preparation and validation. To the best of our knowledge, there is no single tool integrates all types of lithography-compliant check in standard cell libraries validation flow. In this work, we will demonstrate multiple lithography-compliant verification for standard cell library development flow. Validation flow and detailed algorithm implementation will be explained to assist engineers to achieve full lithography-compliant standard cell libraries. An area-efficient standard cell placement methodology will also be discussed to validate the issues arises from standard cell abutment., Comment: Synopsys User Group Silicon Valley (SNUG) 2017

Pattern matching design verification has gained noticeable attention in semiconductor technologies as it can precisely identify more localized problematic areas (weakpoints) in the layout. To address these weakpoints, engineers adopt 'Rip-up and Reroute' methodology to reroute the nets and avoid these weakpoints. However, the technique is unable to address weakpoints due to the cell placement. The only present approach is to manually shift or flip the standard cells to eradicate the weakpoint. To overcome the challenge in going from a manual and laborious process to a fully automated fixing, we have proposed an in-design auto-fixing feature, tested with the commercial design tool, Synopsys IC Compiler. Our experimental result has demonstrated close to one hundred percent lithography weakpoints fixing on all of our 14nm designs.

As compared to DRC rules, DFM rules are a list of selected recommended rules which aim to improve the design margins for better manufacturability. In GLOBALFOUNDRIES, we use DFM scoring methodology as an effective technique to analyze design quality in terms of manufacturability. Physical design engineers can perform our Manufacturability Check Deck (MCD) to asset their design quality during the sign-off stage. In the past, Synopsys users have to convert their design though milkyway database to GDSII format and execute the verification through the third party EDA tools. This method is costly and time-consuming for our Synopsys users. Today, we propose a new and easy-to-use integrated flow which leverages on the ICV engine to provide DFM scoring and in-design fixing techniques. The new methodology address DFM violations early in the design flow and achieve DFM compliance design during sign-off phase.

While standard cell layouts are drawn with minimum design rules for maximum benefit of design area shrinkage, the complicated design rules begin to cause difficulties with signal routes accessing the pins in standard cell layouts. Multiple design iterations are required to resolve routing issues, thus increasing the runtime and the overall chip area. To optimize the chip performance, power and area (PPA) and improve the routability, it is necessary to consider the pin accessibility during standard cell development phase so that each cell is designed to maximize the number of feasible pin-access solutions available to the router. As part of the Synopsys IC Compiler Library Preparation Reference Methodology, the Synopsys Pin Access Checker (PAC) reports DRC violations associated with the standard cell. Based on Synopsys PAC's methodology, we demonstrate several methods to improve the probability of detecting pin accessibility issues, such as reducing the number of cells required for each Synopsys 'testcell', increasing the complexity of the pin connectivity assignment and recommending the router constraints.