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Sub-micrometer thin-film transistors (TFTs) are realized using multi-level imprint lithography. Amorphous indium gallium zinc oxide ( $\alpha $ -IGZO) TFTs with channel lengths as small as $0.7~\mu \text{m}$ , field-effect mobility of 10 cm2V−1s−1 and on/off ratio of circa 107 were integrated into a 1000-pixels per inch (ppi) TFT backplane array. The reduction of the number of patterning steps and the inherent self-registration of the most critical transistor layers on top of each other offer a cost-effective high-throughput fabrication route for high-resolution TFT arrays.

Thin film transistors (TFTs) are the basis for current AMOLED display arrays. For next-generation displays, higher resolution and cost-effective manufacturing of panels is adamant. The current benchmark patterning method in the display industry is photolithography. Here, we propose the use of a hybrid approach of nanoimprint lithography and conventional FPD processing for the realization of high-resolution display backplanes. We demonstrate the realization of sub-micron amorphous oxide semiconductor TFTs with multi-level nanoimprint lithography in order to decrease the number of patterning steps in display manufacturing. Top-gate self-aligned a-IGZO TFTs are realized with performance comparable to benchmark photolithography-based TFTs.

We combine a low dark current and high-detectivity near-infrared (NIR)-sensitive organic photodetector with a high-resolution 508 pixels per inch (ppi) oxide thin-film transistor (TFT) backplane to create a large-area thin NIR detector, using processes that are compatible with flat-panel display fabrication. The detector is characterized showing high uniformity and linearity. With the use of a NIR light source, the detector is capable of imaging the (pattern of) veins under the skin in reflection, leading to improved biometric authentication.

We present a qHD (960 × 540 with three sub-pixels) top-emitting active-matrix organic light-emitting diode display with a 340-ppi resolution using a self-aligned IGZO thin-film transistor backplane on polyimide foil with a humidity barrier. The back plane process flow is based on a seven-layer photolithography process with a CD = 4 μm. We implement a 2T1C pixel engine and use a commercial source driver IC made for low-temperature polycrystalline silicon. By using an IGZO thin-film transistor and leveraging the extremely low off current, we can switch off the power to the source and gate driver while maintaining the image unchanged for several minutes. We demonstrate that, depending on the image content, low-refresh operation yields reduction in power consumption of up to 50% compared with normal (continuous) operation. We show that with the further increase in resolution, the power saving through state retention will be even more significant.

Thin-film transistors (TFTs) are the fundamental building blocks of today’s display industry. To achieve higher drive currents and device density, it is essential to scale down the channel lengths of TFTs. To be able to fabricate short-channel TFTs in large volumes is also equally important in order to realize lower fabrication costs and higher throughput. In this paper, we demonstrate the application of substrate conformal imprint lithography (SCIL) to pattern top-gate (TG) self-aligned (SA) amorphous indium gallium zinc oxide TFTs down to channel length ${L}_{\textsf {G}} = \textsf {450}$ nm with good device scaling properties resulting in average field-effect mobility ( ${\mu }_{FE}$ ) $= \sim 10$ cm $^{\textsf {2}}\cdot \text{V}^{-\textsf {1}}\cdot \text{s}^{\textsf {-1}}$ , ${V}_{\mathrm{ON}} = \,\sim 0.5$ V, and subthreshold swing (SS) $= \sim 0.3$ V/decade. The device performance as a function of channel length outlines the importance of dopant diffusion control for realizing submicrometer SA TFTs. The results demonstrate the compatibility of SCIL-based large-area patterning for the realization of submicrometer TG SA TFTs with a potential for high throughput.

A fast, 128-b implementation of both SRAM and LPROM with integrated periphery in a thin-film amorphous indium–gallium–zinc oxide technology is reported. The SRAM block can be read in 265 $\mu \text{s}$ /byte and written in 110 $\mu \text{s}$ /byte, consumes 12.3 mW, and has an area of 11.9 mm2. Furthermore, after power down, an SRAM memory state retention time of 83 s is shown. The LPROM can be read in 40 $\mu \text{s}$ /b, consumes 4.50 mW, and has an area of 3.75 mm2. The SRAM enables fast volatile RAM memory for thin-film microprocessors, while the LPROM can be used to store the identification code for state-of-the-art thin-film RFID tags.

Materials / Molecular Diversity Preservation International 6(9), 3710-3726 (2013). doi:10.3390/ma6093710, Published by MDPI, Basel

We present a qHD (960x540 with 3 sub-pixels) top-emitting AMOLED display with 340ppi resolution using a self-aligned (SA) IGZO TFT backplane on polyimide-foil with humidity barrier. The back plane process flow is based on a 7 layer photolithography process with a CD=4um. We implement a 2T1C pixel engine and use commercial source driver IC made for LTPS. By using IGZO TFT and leveraging the extremely low off-current, we can switch-off the power to the source and gate driver while maintaining the image un-changed for several minutes. We demonstrate that, depending on the image content, low-refresh operation yields reduction in power consumption of up to 50% compared to normal (continuous) operation. We show that with further increase in resolution, the power saving through state retention will be even more significant.

Flexible electronics is a growing field and is currently maturing in applications such as displays, smart packaging, organic light-emitting diodes and organic photovoltaic cells. In order to process on flexible substrates at high throughput and large areas, novel patterning techniques will be essential. Conventional optical lithography is limited in throughput as well as resolution, and requires several alignment steps to generate multi-layered patterns, required for applications such as thin-film transistors. It therefore remains a complex and expensive process. Nanoimprint lithography is an emerging alternative to optical lithography, demonstrating patterning capabilities over a wide range of resolutions, from several microns down to a few nanometres. For display applications, nanoimprint lithography can be used to pattern various layers. Micron sized thin-film transistors for backplane can be fabricated where a self-aligned geometry is used to decrease the number of alignment steps, and increase the overlay accuracy. In addition, nano-structures can be used for optical applications such as anti-reflective surfaces and nano patterned transparent electrodes. Imprint lithography is a fully roll-to-roll compatible process and enables large area and high throughput fabrication for flexible electronics. In this paper we discuss the possibilities and the challenges of large area patterning by roll-to-roll nanoimprint lithography, reviewing micron and nano sized structures realized on our roll-to-roll equipment. Nano patterned transparent electrodes, moth-eye antireflective coatings, and multilevel structures will be covered.