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The advent of machine learning (ML) methods for the industry has opened new possibilities in the automotive domain, especially for Advanced Driver Assistance Systems (ADAS). These methods mainly focus on specific problems ranging from traffic sign and light recognition to pedestrian detection. In most cases, the computational resources and power budget found in ADAS systems are constrained while most machine learning methods are computationally intensive. The usual solution consists in adapting the ML models to comply with the memory and real-time (RT) requirements for inference. Some models are easily adapted to resource-constrained hardware, such as Support Vector Machines, while others, like Neural Networks, need more complex processes to fit into the desired hardware. The ADAS hardware (HW platforms) are diverse, from complex MPSoC CPUs down to classical MCUs, DPSs and application-specific FPGAs and ASICs or specific GPU platforms (such as the NVIDIA families Tegra or Jetson). Therefore, there is a tradeoff between the complexity of the ML model implemented and the selected platform that impacts the performance metrics: function results, energy consumption and speed (latency and throughput). In this paper, a survey in the form of systematic review is conducted to analyze the scope of the published research works that embed ML models into resource-constrained implementations for ADAS applications and what are the achievements regarding the ML performance, energy and speed trade-off.

Gait analysis has evolved significantly during last years due to the great development of the Medical Internet of Things (MIoT) platforms that allow an easy integration of sensors (inertial, magnetic and pressure in our case) to the complex analytics required to compute, not only relevant parameters, but also meaningful indexes. In this paper, we extend a previous development based on a fully wireless pair of insoles by implementing an updated version with more reliable and user-friendly devices, smartphone app and web front-end and back-end. We also extend previous work focused on fall analysis (with the corresponding fall risk index or FRI) with the proposal of a new surgery recovery index (SRI) to account for the individual speed recovery speed that can be measured either at clinical facilities or at home in a telemedicine environment or while doing daily life activities. This new index can be personalized for different types of surgeries that affect gait such as hip, knee, etc. This paper presents the case of hip recovery and is built on top of the clinical standard SPPB test and allows obtaining quantitative parameters directly from the sensors.

Augmented reality is showing a continuous evolution due to the increasing number of smart glasses that are being used for different applications (e.g. training, marketing, industry, risk avoidance, etc.). In this paper, we present an implementation that uses augmented reality (AR) for emergency situations in smart buildings by means of indoor localization through the use of sub-GHz beacons. This also includes the mapping of emergency elements in the three-dimensional building, together with some example cases.

Pedestrian detection is one of the key problems in the emerging self-driving car industry. In addition, the Histogram of Gradients (HOG) algorithm proved to provide good accuracy for pedestrian detection. Many research works focused on accelerating HOG algorithm on FPGA (Field-Programmable Gate Array) due to its low-power and high-throughput characteristics. In this paper, we present an energy-efficient HOG-based implementation for pedestrian detection system on a low-cost FPGA system-on-chip platform. The hardware accelerator implements the HOG computation and the Support Vector Machine classifier, the rest of the algorithm is mapped to software in the embedded processor. The hardware runs at 50 Mhz (lower frequency than previous works), thus achieving the best pixels processed per clock and the lower power design.

Ajudes: National Key Research and Development Program of "Strategic Advanced Electronic Materials" under Grant 2016YFB0401100 and in part by the NSFC of China under Grant 61274083 and Grant 61334008. Attributed to its advantages of super mechanical flexibility, very low-temperature processing, and compatibility with low cost and high throughput manufacturing, organic thin-film transistor (OTFT) technology is able to bring electrical, mechanical, and industrial benefits to a wide range of new applications by activating nonflat surfaces with flexible displays, sensors, and other electronic functions. Despite both strong application demand and these significant technological advances, there is still a gap to be filled for OTFT technology to be widely commercially adopted. This paper providesa comprehensive reviewof the current status of OTFT technologies ranging from material, device, process, and integration, to design and system applications, and clarifies the real challenges behind to be addressed.

We report on the development of inkjet-printed thin-film resistors using both organic and inorganic ink formulations. The passive devices were manufactured on flexible polymer substrates in ambient condition without the need for a cleanroom environment or inert atmosphere and at a maximum temperature of 150 °C. By using the same manufacturing process, the rapid electrical sintering (RES) method is demonstrated as effective for the fabrication of inkjet-printed, programmable Write-Once-Read-Many (WORM) memories. Several hundred fully inkjet-printed resistors with different parameters were fabricated and subsequently morphologically and electrically characterized with the aim of obtaining statistically significant data. From a manufacturing process viewpoint, the procedures based on inkjet printing herein described are highly attractive: they do not require high temperatures, low pressures, special atmospheric conditions, and any masks, therefore providing a versatile low-cost approach to fabricate passive electrical components and simple circuits useful for the electronic industry. Printing can be carried out at a sufficiently low temperature to avoid damage to the fabric substrate and these devices can be used in a range of applications requiring flexible and conformal devices from embedded passive filters in PCBs to wearable electronics.

The objective of the present research is to observe to what extent the stereoscopic effect presents a solution for enhancement of user interactions in the Web context. This paper describes an experiment conducted to detect differences in perception between 2D and 3D graphical user interfaces of an e-Commerce web application. The results of the conducted user study among 39 participants indicate significantly higher performance of the 2D interface in terms of efficiency, satisfaction, and, consequently, overall usability. Therefore, for the studied sample, the stereoscopic effect had mostly negative impact on user interactions. El objetivo de la presente investigación es observar hasta qué punto el efecto estereoscópico es una solución para mejorar la interacción del usuario en el contexto Web. Se describe un experimento llevado a cabo para detectar diferencias de percepción entre las interfaces gráficas de usuario 2D y 3D de una aplicación web de comercio electrónico. Los resultados del estudio de usuarios, llevado a cabo con 39 participantes, indican un rendimiento significativamente más alto de la interfaz 2D en términos de eficiencia, satisfacción y, en consecuencia, facilidad de uso general. Por lo tanto, para la muestra estudiada, el efecto estereoscópico tuvo un impacto mayormente negativo en las interacciones del usuario.

This article describes the web application called S3Doodle. It is an initial example of the combination of a stereoscopic graphical user interface that produces stereoscopic content and is controlled by hand gestures. The web application uses core stereo 3D concepts and implements them with cutting edge technology to create a differentiated experience. We use a spatial input control as an interface that allows us to introduce depth into the created compositions. S3Doodle’s creation is documented, and the experience we had while building it is explained, shedding light on which are the technical decisions behind. We also gather user’s comments from the utilization of the web app. This application serves us as a case study for exploring gestural and stereo interactions, from which we get initial reactions upon which we can provide a better experience for future applications.

Detection of QRS complexes in ECG signals is required to determine heart rate, and it is an important step in the study of cardiac disorders. ECG signals are usually affected by noise of low and high frequency. To improve the accuracy of QRS detectors several methods have been proposed to filter out the noise and detect the characteristic pattern of QRS complex. Most of the existing methods are at a disadvantage from relatively high computational complexity or high resource needs making them less optimized for its implementation on portable embedded systems, wearable devices or ultra-low power chips. We present a new method to detect the QRS signal in a simple way with minimal computational cost and resource needs using a novel non-linear filter.

The operational stability of all-inkjet printed transistors is reported. At room temperature the threshold voltage shifts following a stretched exponential with a relaxation time τ=1x103 s. Two distinct trap sites active in different temperature ranges, one at 200-250 K and other above 310 K cause the electrical instability. Both types of traps capture holes and can be fast neutralized by photogenerated electrons. Optically induced detrapping currents confirm the differences in trap signature. It is proposed, that the traps have a common physical origin related to water.

Reconfigurable parallel computing is required to provide high-performance embedded computing, hide hardware complexity, boost software development, and manage multiple workloads when multiple applications are running simultaneously on the emerging network-on-chip (NoC)-based multiprocessor systems-on-chip (MPSoCs) platforms. In these type of systems, the overall system performance may be affected due to congestion, and therefore parallel programming stacks must be assisted by quality-of-service (QoS) support to meet application requirements and to deal with application dynamism. In this paper, we present a hardware-software QoS-driven reconfigurable parallel computing framework, i.e., the NoC services, the runtime QoS middleware API and our ocMPI library and its tracing support which has been tailored for a distributed-shared memory ARM clustered NoC-based MPSoC platform. The experimental results show the efficiency of our software stack under a broad range of parallel kernels and benchmarks, in terms of low-latency interprocess communication, good application scalability, and most important, they demonstrate the ability to enable runtime reconfiguration to manage workloads in message-passing parallel applications.

Inkjet printing is a promising and challenging technique that could potentially revolutionize large area and organic electronics fabrication. Inkjet systems are designed to construct devices and circuits drop by drop, which would lead to a new paradigm in electronics fabrication. However, inkjet technology for Printed Electronics is still under development and several challenges remain. While there is significant progress being made in the development of electronic devices, such as transistors or sensors, there is a lack of work on circuit and system level design. Designing devices and circuits implies a wide knowledge of process aspects, requiring a complex interaction among concepts, tools and processes coming from different science and engineering disciplines. An explicit methodology is needed to separate design from fabrication in a similar way as in silicon design, to design devices and systems without a deep knowledge of process and materials; thus making it possible to open up inkjet technology to a larger community and undergo more rapid design implementations. In this paper we present the main aspects of such a methodology and we discuss the key topics on inkjet technology that allow us to propose these new specific steps.

Embedded multimedia devices are now a common element of our environment, such as mp3 players, handheld devices, and so on. Choosing the right main processing element is a key issue for the success of these devices, and their consumption, performance, retargetability, and development time are some of the elements that need to be analyzed and well-balanced. In this paper, we map the same multimedia application (MPEG-4 main profile) into various target platforms generally used in the embedded area. The design flow of our work starts with a single MPEG-4 encoder description which is later refined and optimized to be implemented on different platforms: an embedded platform formed by a high performance digital signal processor and an embedded processor, an application specific instruction processor, a specific hardware implemented in a field-programmable gate array for accelerating the data-flow part of the system with a soft-core for the control part, and an application specific integrated circuit. The main contribution of this paper is to illustrate a methodology that can be generalized to different data dominant applications. This paper describes a new methodology to obtain near optimal implementation from concept to silicon for all platforms and it can be extended to any hybrid HW/SW multimedia platform. We evaluate the different transformations of each platform to arrive at an optimal implementation. These higher level transformations allow achieving better results than using more precise efforts in mapping the design in the physical level. This methodology can be extended to any data dominant application.

Wearable electronics are gaining widespread use as enabling technologies, monitoring human physical activity and behavior as part of connected health infrastructures. Attention to human factors and comfort of these devices can greatly positively influence user experience, with a subsequently higher likelihood of user acceptance and lower levels of device rejection. Here, we employ a human factors and comfort assessment methodology grounded in the principles of human-centered design to influence and enhance the design of an instrumented insole. A use case was developed and interrogated by stakeholders, experts, and end users, capturing the context of use and user characteristics for the instrumented insole. This use case informed all stages of the design process through two full design cycles, leading to the development of an initial version 1 and a later version 2 prototype. Each version of the prototype was subjected to an expert human factors inspection and controlled comfort assessment using human volunteers. Structured feedback from the first cycle of testing was the driver of design changes implemented in the version 2 prototype. This prototype was found to have significantly improved human factors and comfort characteristics over the first version of the prototype. Expert inspection found that many of the original problems in the first prototype had been resolved in the second prototype. Furthermore, a comfort assessment of this prototype with a group of young healthy adults showed it to be indistinguishable from their normal footwear. This study demonstrates the power and effectiveness of human factors and comfort assessment methodologies in influencing and improving the design of wearable devices. This work was part funded by the EU FP7 project WIISEL (Wireless Insole for Independent and Safe Elderly Living). Project number FP7-ICT-2011-288878. peer-reviewed

This paper presents a global proposal and methodology for developing digital printed electronics (PE) prototypes, circuits and application specific printed electronics circuits (ASPECs). We start from a circuit specification using standard Hardware Description Languages (HDL) and executing its functional simulation. Then we perform logic synthesis that includes logic gate minimization by applying state-of-the-art algorithms embedded in our proposed electronic design automation (EDA) tools to minimize the number of transistors required to implement the circuit. Later technology mapping is applied, taking into account the available technology, (i.e., PMOS only technologies) and the cell design style (either Standard Cells or Inkjet Gate Array). These layout strategies are equivalent to those available in application specific integrated circuits (ASICs) flows but adapting them to Printed Electronics, which vary greatly depending on the targeted technology. Then Place & Route tools perform floorplan, placement and wiring of cells, which will be checked by the corresponding layout versus schematic (LVS). Afterwards we execute an electrical simulation including parasitic capacitances and relevant parameters. Finally, we obtain the prototypes which will be characterized and tested. The most important aspect of the proposed methodology is that it is portable to different PE processes, so that considerations and variations between different fabrication processes do not affect the validity of our approach. As final results, we present fabricated prototypes that are currently being characterized and tested.

Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as "Bridging Platform". This transfer to "Bridging Platform" from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit.

We report about the use of a printed pentafluorothiophenol layer on top of the dielectric surface as a passivation coating to improve the operational stability of all-ink-jet printed transistors. Transistors with bottom-gate structure were fabricated using cross-linked poly-4-vinylphenol (c-PVP) as dielectric layer and an ink formulation of an amorphous triarylamine polymer as semiconductor. The resulting TFTs had low turn-on voltage (Vth < |5 V|) and a mobility ≈0.1 cm2/(V s). A comparison of identically fabricated transistors shows that devices with coated dielectric have a higher operational stability than those using bare c-PVP. This conclusion is supported by a quantitative study of the threshold voltage shift with time under continuous operation. Long exposure to the ambient atmosphere causes an increase in the threshold voltage strongly dependent on the used semiconducting ink formulation. © 2015 Elsevier Ltd.

The Local Group galaxies constitute a fundamental step in the definition of cosmic distance scale. Therefore, obtaining accurate distance determinations to the galaxies in the Local Group, and notably to the Andromeda Galaxy (M31), is essential to determining the age and evolution of the Universe. With this ultimate goal in mind, we started a project to use eclipsing binaries as distance indicators to M31. Eclipsing binaries have been proved to yield direct and precise distances that are essentially assumption free. To do so, high-quality photometric and spectroscopic data are needed. As a first step in the project, broad band photometry (in Johnson B and V) has been obtained in a region (34'x34') at the North-Eastern quadrant of the galaxy over 5 years. The data, containing more than 250 observations per filter, have been reduced by means of the so-called difference image analysis technique and the DAOPHOT program. A catalog with 236238 objects with photometry in both B and V passbands has been obtained. The catalog is the deepest (V, 12 pages, 9 figures; accepted for publication in A&A; see electronic tables and full resolution images at http://www.am.ub.es/~fvilarde/download/A+A/

All inkjet printed rectifying diodes based on a metal-insulator-semiconductor (MIS) layer stack are presented. The rectifying properties were optimized by careful selection of the insulator interlayer thickness and the layout structure. The different diode architectures based on the following materials are investigated: (1) silver/ poly (methylmethacrylate-methacrylic acid)/ polytriarylamine/ silver, (2) silver/ polytriarylamine/ poly (methylmethacrylate-methacrylic acid)/ silver, and (3) silver/ poly (methylmethacrylate-methacrylic acid)/ poly-triarylamine/ poly(3,4-ethylenedioxythiophene) poly (styrenesulfonate). The MIS diodes show an averaged rectification ratio of 200 and reasonable forward current density reaching 40 mA cm -2. They are suitable for a number of applications in flexible printed organic electronics. EU [287682]

The fabrication of pH-sensitive ISFET devices in an unmodified two-metal commercial CMOS technology (1.0 um from Atmel-ES2) is reported. The ISFET devices have a gate structure compatible with the CMOS process, with an electrically floating electrode consisting on polysilicon plus the two metals. The passivation oxynitride layer acts as the pH-sensitive material in contact with the liquid solution. The devices have shown good operating characteristics, with a 47 mV/pH response. The use of a commercial CMOS process allows the straightforward integration of signal-processing circuitry. An ISFET amplifier circuit has been integrated with the ISFET sensors.

To allow real performance-driven logic synthesis, area, power and delay trade-off should be considered from the very early stages of the synthesis process. Accurate models must be provided for area occupation, delay, and power dissipation. Moreover, the model parameters should be available during all stages of logic synthesis. In this paper we present the models and derive cost functions to calculate their parameters. At the early stages of logic synthesis, generic cell library information and statistical data extracted from real integrated circuits (IC) are used to calculate the model parameters. As the synthesis process progress, technology dependent information becomes available and the model parameters are gradually refined.

Ambient Intelligence is a new paradigm in which environments are sensitive and responsive to the presence of people. This is having an increasing importance in multimedia applications, which frequently rely on sensors to provide useful information to the user. In this context, multimedia applications must adapt and personalize both content and interfaces in order to reach acceptable levels of context-specific quality of service for the user, and enable the content to be available anywhere and at any time. The next step is to make content available to everybody in order to overcome the existing access barriers to content for users with specific needs, or else to adapt to different platforms, hence making content fully usable and accessible. Appropriate access to video content, for instance, is not always possible due to the technical limitations of traditional video packaging, transmission and presentation. This restricts the flexibility of subtitles and audio-descriptions to be adapted to different devices, contexts and users. New Web standards built around HTML5 enable more featured applications with better adaptation and personalization facilities, and thus would seem more suitable for accessible AmI environments. This work presents a video subtitling system that enables the customization, adaptation and synchronization of subtitles across different devices and multiple screens. The benefits of HTML5 applications for building the solution are analyzed along with their current platform support. Moreover, examples of the use of the application in three different cases are presented. Finally, the user experience of the solution is evaluated.

Following EU directives on Media Access and Ambient Assisted Living, the broadcasting industry needs to introduce new services in order to guarantee access to all citizens. The article and its conclusions are part of the EU project DTV4ALL, which focuses on some possible broadcasting scenarios for achieving barrier-free television for those with visual impairments. Five enhanced Audiodescription (AD) scenarios were proposed and evaluated: 1) Live streaming Internet TV with AD, 2) AD reception in a group situation, 3) Video on demand over a set-top-box, 4) Video on PC and 5) Podcasts. User evaluation concerning usefulness, quality and usability of the services was assessed using questionnaires. Results of the user evaluation show that not only are AD emerging services technically viable but they are also positively rated by users. Implementation of these services will provide improved access to content, making TV accessible for all.

We present preliminary work in the field of saving and restoring model state within a SystemC simulation environment. Save and Restore (or checkpointing) is a useful technique that can greatly assist target software and simulation model development and debug. In contrast to other approaches that aim at saving and restoring the state of an entire simulation process, we investigate mechanisms by which only the essential simulation state is saved. This makes the checkpoints far more compact, and saved simulation states can be moved between host machines, and be used with updated or completely different simulation models. Our results indicate that SystemC models written to certain coding guidelines can be saved and restored reliably. As a result, virtual platforms and platform components written in SystemC can be made more useful to software developers, and support smarter workflows.

We introduce a learning algorithm for feed-forward neural networks with synapses which can only take a discrete number of values. Taking into account the inherent limitations associated to these networks, we think that the performance of the method is quite efficient as we have shown through some simple results. The main novelty with respect to other discrete learning techniques is a different strategy in the search for solutions. Generalizations to any arbitrary distribution of discrete weights are straightforward.

This paper presents a method to automatically recognize and model singleand multi-output logic gates out of a switch-level network, even for irregular transistor structures. Resulting subcircuit models are directly used in a symbolic simulator for circuit analysis purposes. Other applications of derived netlists cover switch-level simulation acceleration and test generation tool enhancement.

The evolution of microeletronic design techniques implies an important methodological effort to increase the degree of abstraction far from technology and devices. This process is not uniform and depends on the specific electronic domains. As for sensors and actuators, there has been quite a few approaches toward this global system design methodologies, and most of them in the last years. The main points for this relative delay are: non-standard technological processes specially in case of embedded microsystems, different types of analysis required, that use different environments for each magnitude (mechanics, flow, magnetic,..), connection between circuit and structural 3D simulators, whose representations need to be abstracted by introducing the concept of sensor cell libraries, to estimate performance in the global system (large areas, signal sensitivities, mechanical restrictions,...). In the paper, we show the choices we select for these decisions in the case of a new microsystem fabrication process for embedded microsystems, developed together with the tool and design methodology, based on the 1.0µm CMOS from ATMEL-ES2. Some demonstrators are presented, together with measurement results.

Nowadays industrial monoprocessor and multipro- cessor systems make use of hardware floating-point units (FPUs) to provide software acceleration and better precision due to the necessity to compute complex software applications. This paper presents the design of an IEEE-754 compliant FPU, targeted to be used with ARM Cortex-M1 processor on FPGA SoCs. We face the design of an AMBA-based decoupled FPU in order to avoid changing of the Cortex-M1 ARMv6-M architecture and the ARM compiler, but as well to eventually share it among different processors in our Cortex-M1 MPSoC design. Our HW- SW implementation can be easily integrated to enable hardware- assisted floating-point operations transparently from the software application. This work reports synthesis results of our Cortex-M1 SoC architecture, as well as our FPU in Altera and Xilinx FPGAs, which exhibit competitive numbers compared to the equivalent Xilinx FPU IP core. Additionally, single and double precision tests have been performed under different scenarios showing best case speedups between 8.8x and 53.2x depending on the FP operation when are compared to FP software emulation libraries.

Semantic Search and Ontologies are one of the key technologies that can improve content management. Nonetheless, in order to be widely diffused, these technologies lack real-time capabilities, that speed up both the indexing and the retrieval processes. This contribution presents the approach and strategy proposed to tackle this problem, within the Spanish project E-Sentencias; a project for the development of a management system for lawyers that includes documentation and multimedia related to the management of their legal cases

Printed electronics technologies add new fabrication concepts to the classical set of microelectronic processes. Among these, the use of digital printing techniques such as inkjet permits the deposition of materials on top of preexisting substrates without any mask. This allows individual personalization of electronic circuits. Different proposals have been made to make use of such a property: (1) wiring new metallic layers on top of circuits to build programmable logic array-like circuits, (2) programming OTP ROM like memories, and (3) building inkjet-configurable gate arrays. The capability of building an individual circuit with technological steps simpler than photolithographic ones opens a concept similar to the successful field programmable gate array. Although nowadays the process resolution is still low, it can quickly evolve to higher wiring densities and therefore permit a greater level of transistor integration. In this paper, we propose a new structure to realize the connections only by deposition of conductive dots oriented to optimize the area needed to implement the drop-on-demand (DoD) wiring at circuit level. One important feature of this structure is that it minimizes the amount of printed material required for the connection thereby reducing failures often seen with DoD printing techniques for conductive lines. These structures have been validated by two different DoD technologies: inkjet and superfine jet, and have been compared to mask-based photolithography technology with promising results. acceptedVersion

Search, retrieval, and management of multimedia contents are challenging tasks for users and researchers alike. The aim of e-sentencias Project is to develop a software-hardware system for the global management of the multimedia contents produced by the Spanish Civil Courts. We apply technologies such as the Semantic Web, ontologies, NLP techniques, audio-video segmentation and IR. The ultimate goal is to obtain an automatic classification of images and segments of the audiovisual records that, coupled with textual semantics, allows anefficient navigation and retrieval of judicial documents and additional legal sources.