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A comprehensive overview of PowderMEMS—a novel back-end-of-line-compatible microfabrication technology—is presented in this paper. The PowderMEMS process solidifies micron-sized particles via atomic layer deposition (ALD) to create three-dimensional microstructures on planar substrates from a wide variety of materials. The process offers numerous degrees of freedom for the design of functional MEMSs, such as a wide choice of different material properties and the precise definition of 3D volumes at the substrate level, with a defined degree of porosity. This work details the characteristics of PowderMEMS materials as well as the maturity of the fabrication technology, while highlighting prospects for future microdevices. Applications of PowderMEMS in the fields of magnetic, thermal, optical, fluidic, and electrochemical MEMSs are described, and future developments and challenges of the technology are discussed. [ABSTRACT FROM AUTHOR]

This paper reviews state-of-the-art design approaches for low-voltage radio frequency (RF) and millimeter-wave (mm-wave) CMOS circuits. Effective design techniques at RF/mm-wave frequencies are described, including body biasing in fully depleted (FD) silicon-on-insulator (SOI) CMOS technologies and circuit topologies based on integrated reactive components (i.e., capacitors, inductors and transformers). The application of low-voltage design techniques is discussed for the main RF/mm-wave circuit blocks, i.e., low-noise amplifiers (LNAs), mixers and power amplifiers (PAs), highlighting the main design tradeoffs. [ABSTRACT FROM AUTHOR]

This article investigates the gallium nitride based bridgeless dual single-ended primary inductor converter (SEPIC) power factor correction (PFC) with full input voltage range zero-voltage-switching (ZVS) turn-on for the application of step down ac–dc converter. The operation principle for the bridgeless Dual-SEPIC PFC and the theoretical analysis for the ZVS operation has been investigated. Furthermore, a new magnetic integration has been proposed to assemble all three inductors, including one input inductor and two output side inductors into one E-I-E core. The integrated inductor reduces the total ferrite volume and makes the converter more compact. The inductance design for ZVS SEPIC PFC and the magnetic reluctance modeling for the E-I-E core with the coupled inductor has been analyzed. The effective equivalent inductance of the input inductor can be implemented with a much less number of turns by a carefully designed coupling coefficient. Finally, a 300 W GaN-based MHz bridgeless dual-SEPIC PFC with the integrated inductors is developed and tested with full–range ZVS, 97% peak efficiency based on the ZVS extension strategy. [ABSTRACT FROM AUTHOR]

This paper presents a measurement and simulation studies on the near magnetic field radiated by an integrated inductor with magnetic material. It presents the probe influence on the measured magnetic field and the importance of the probe position. These studies are performed in simulation using HFSS software and in measurement using scan near field bench. A very good agreement between measurement and simulation is shown. [ABSTRACT FROM AUTHOR]

This paper reviews state-of-the-art design approaches for low-voltage radio frequency (RF) and millimeter-wave (mm-wave) CMOS circuits. Effective design techniques at RF/mm-wave frequencies are described, including body biasing in fully depleted (FD) silicon-on-insulator (SOI) CMOS technologies and circuit topologies based on integrated reactive components (i.e., capacitors, inductors and transformers). The application of low-voltage design techniques is discussed for the main RF/mm-wave circuit blocks, i.e., low-noise amplifiers (LNAs), mixers and power amplifiers (PAs), highlighting the main design tradeoffs.

In this article, the simulation results, the technological steps of manufacturing, and the characterization results at low and medium frequencies (20 MHz to a few hundred MHz) of integrated inductors with two magnetic layers are presented. Simulation realized with the high-frequency structure simulator (HFSS) software allows the impact of the vertical and horizontal air gaps on the inductance value for inductors with two magnetic layers to be determined. Inductors with two magnetic layers are manufactured with magnetic thicknesses varying from 100 to $500~\mu \text{m}$. The interest of this new manufacturing process is compatible with most ferrite. The measurement results show good agreement with the simulation results. By minimizing the vertical air gap, the inductance value increases with a ratio equal to the relative permeability of the magnetic material when field lines are totally canalized into the magnetic layers. The extracted resistance evolution of the inductor on the frequency is explained by taking into account the skin and proximity effects for the conductor losses and the iron losses for the magnetic material. [ABSTRACT FROM AUTHOR]

High-performance and small-size on-chip inductors play a critical role in contemporary radio-frequency integrated circuits. This work presents a reliable surrogate modeling technique combining low-fidelity EM simulation models, response surface approximations based on kriging interpolation, and space mapping technology. The reported method is useful for the development of broadband and highly accurate data-driven models of integrated inductors within a practical timeframe, especially in terms of the computational expense of training data acquisition. Application of the constructed surrogate model for rapid design optimization of a compact on-chip inductor is demonstrated. The optimized EM-validated design solution can be reached at a low computational cost, which is a considerable improvement over existing approaches. In addition, this work provides a description and illustrates the usefulness of a multi-fidelity design optimization method incorporating EM computational models of graduated complexity and local polynomial approximations managed by an output space mapping optimization framework. As shown by the application example, the final design solution is obtained at the cost of a few high-fidelity EM simulations of a small-size integrated coil. A supplementary description of variable-fidelity EM computational models and a trade-off between model accuracy and its processing time complements the work.

Ultra-low profile integrated magnetic solenoid inductors and transformers were fabricated on 200 mm wafers with back end of line (BEOL) techniques. The process uses thick copper metallization, polymer coating, and laminated amorphous Co–Zr–Ta magnetic material. The substrate was thinned to obtain an inductor thickness of $150~\mu \text{m}$. By varying the core size and winding pitch, a large set of inductance values was obtained, from 20 to 500 nH in the 1 MHz to 3 GHz frequency range. We report a record inductance surface density of $3500\,\,\text {nH}\cdot \text {mm}^{\mathrm {-2}}$ and quality factors up to 23, and transformers with high coupling factors (>0.95). [ABSTRACT FROM AUTHOR]

In this paper, an analysis of the methodologies proposed in the past years to automate the synthesis of radio-frequency (RF) integrated circuit blocks is presented. In the light of this analysis, and to avoid nonsystematic iterations between sizing and layout design steps, a multiobjective optimization-based layout-aware sizing approach with preoptimized integrated inductor(s) design space is proposed. An automatic layout generation from netlist to ready-to-fabricate prototype is carried in-the-loop for each tentative sizing solution using an RF-specific module generator, template-based placer and evolutionary multinet router with preoptimized interconnect widths. The proposed approach exploits the full capabilities of the most established computer-aided design tools for RF design available nowadays, i.e., RF circuit simulator as performance evaluator, electromagnetic simulator for inductor characterization, and layout extractor to determine the complete circuit layout parasitics. Experiments are conducted over a widely used circuit in the RF context, showing the advantages of performing complete layout-aware sizing optimization from the very initial stages of the design process. [ABSTRACT FROM AUTHOR]

This paper presents integrated inductors with Co-Zr-Ta-B (CZTB) thin films on flexible organic substrates for MHz–GHz applications. This paper demonstrated the fabrication and characterization of magnetic thin-film inductors on flexible organic substrates, such as polyimide and Ajinomoto build-up film thin films. These films have thicknesses of only tens of micrometer and thus are very flexible compared to the same inductor structures fabricated on rigid substrates, such as quartz. The magnetic films on flexible substrates were observed to maintain similar magnetic properties compared with those on Si substrate, but with greater coercivity likely due to the increased roughness of the substrate surface. The fabricated thin-film inductors on organic substrates with inductance $L$ , measured by RF characteristics, have shown significantly increased inductance compared to air-core inductors (without magnetic core materials). This paper also demonstrated a high frequency response, clearly over GHz, consistent with the CZTB type of materials. The frequency response, as well as inductance and Q values, remains similar even after many iterations of bending to a large degree, indicating the robustness of the inductor on flexible organic substrates, as well as that of the magnetic thin films. [ABSTRACT FROM AUTHOR]

In recent years, the application of evolutionary computation techniques to electronic circuit design problems, ranging from digital to analog and radiofrequency circuits, has received increasing attention. The level of maturity runs inversely to the complexity of the design task, less complex in digital circuits, higher in analog ones and still higher in radiofrequency circuits. Radiofrequency inductors are key culprits of such complexity. Their key performance parameters are inductance and quality factors, both a function of the frequency. The inductor optimization requires knowledge of such parameters at a few representative frequencies. Most common approaches for optimization-based radiofrequency circuit design use analytical models for the inductors. Although a lot of effort has been devoted to improve the accuracy of such analytical models, errors in inductance and quality factor in the range of 5%–25% are usual and it may go as high as 200% for some device sizes. When the analytical models are used in optimization-based circuit design approaches, these errors lead to suboptimal results, or, worse, to a disastrous non-fulfilment of specifications. Expert inductor designers rely on iterative evaluations with electromagnetic simulators, which, properly configured, are able to yield a highly accurate performance evaluation. Unfortunately, electromagnetic simulations typically take from some tens of seconds to a few hours, hampering their coupling to evolutionary computation algorithms. Therefore, analytical models and electromagnetic simulation represent extreme cases of the accuracy-efficiency trade-off in performance evaluation of radiofrequency inductors. Surrogate modeling strategies arise as promising candidates to improve such trade-off. However, obtaining the necessary accuracy is not that easy as inductance and quality factor at some representative frequencies must be obtained and both performances change abruptly around the self-resonance frequency, which is particular to each device and may be located above or below the frequencies of interest. Both, offline and online training methods will be considered in this work and a new two-step strategy for inductor modeling is proposed that significantly improves the accuracy of offline methods The new strategy is demonstrated and compared for both, single-objective and multi-objective optimization scenarios. Numerous experimental results show that the proposed two-step approach outperforms simpler application strategies of surrogate modelling techniques, getting comparable performances to approaches based on electromagnetic simulation but with orders of magnitude less computational effort. [ABSTRACT FROM AUTHOR]

A physical-based analytical model for on-chip inductors is developed. A ladder structure is used to model the skin and proximity effects in metal lines. The substrate electric and substrate magnetic losses are accurately modeled by RC and RL ladder structures, respectively. The effective inductance reduction due to the eddy current in the lossy silicon substrate at high frequency is modeled by a negative mutual inductance between the inductor and the substrate. All the model parameters can be calculated from the layout and process parameters. On-chip inductors with different geometries and substrate resistivities were fabricated for the verifications. The measured results are in very good agreement with the proposed model. This generic model can be applied to various substrate resistivities; thus, it is suitable for different technologies. This model can facilitate the design and optimization of on-chip inductors for RF IC applications. [ABSTRACT FROM AUTHOR]

This paper presents an in-depth analysis of the operation of a CMOS single-chip three-dimensional inductor over a MOSFET structure at RF frequencies. Active circuitry is placed underneath the integrated inductors in order to take advantage of the vacant space. Measurements indicate that the operation of the MOSFET and of the inductor is affected in a predictable manner. The paper theoretically investigates the interaction between the two elements, analyzes the origin of all appearing effects and compares the theory with the experimental data from a typical CMOS process. Moreover, this study proposes possible applications and design guides and confirms the attractiveness of the inductor over MOSFET placement. [ABSTRACT FROM AUTHOR]

High-performance and small-size on-chip inductors play a critical role in contemporary radio-frequency integrated circuits. This work presents a reliable surrogate modeling technique combining low-fidelity EM simulation models, response surface approximations based on kriging interpolation, and space mapping technology. The reported method is useful for the development of broadband and highly accurate data-driven models of integrated inductors within a practical timeframe, especially in terms of the computational expense of training data acquisition. Application of the constructed surrogate model for rapid design optimization of a compact on-chip inductor is demonstrated. The optimized EM-validated design solution can be reached at a low computational cost, which is a considerable improvement over existing approaches. In addition, this work provides a description and illustrates the usefulness of a multi-fidelity design optimization method incorporating EM computational models of graduated complexity and local polynomial approximations managed by an output space mapping optimization framework. As shown by the application example, the final design solution is obtained at the cost of a few high-fidelity EM simulations of a small-size integrated coil. A supplementary description of variable-fidelity EM computational models and a trade-off between model accuracy and its processing time complements the work. [ABSTRACT FROM AUTHOR]

Three down-conversion mixers for low-voltage, balanced 900 MHz wireless applications are introduced. The mixers are implemented in a 0.8 μm BiCMOS process and based on the four transistor BJT switching quad widely used in Gilbert cells. The mixers are designed to operate at a supply voltage of 1.5 V and without external components. The implemented mixers have a few decibels of conversion loss, a third-order input intercept point of a few dBm and a single sideband noise figure of about 15 dB. It is demonstrated that modest mixer operation performance is achieved with a DC power consumption of only 1 mW. Also planar inductors on silicon and bond-wire inductors are shown to be valuable to achieve a return loss of about 9 dB for input and output ports of a mixer. The measurement results for the mixers as well as the lumped element models for the used planar inductor and for the bondwire are presented. [ABSTRACT FROM AUTHOR]

A 1.6 GHz fully monolithic silicon bipolar LC current-controlledoscillator (CCO) circuit implemented in a 0.8 µmBiCMOS technology and characterized for use in wireless applicationsis presented. The integrated resonator circuit uses high speed(18 GHz) bipolar transistors, a 14 nH rectangular spiral inductorfabricated by using a standard 2-level metallization, and a widebandpn-varactor structure. Additionally, to save chip area, the integratedcapacitors were fabricated below the planar inductor structure.In order to aid the IC design, a simple equivalent circuit modelfor the integrated inductor on silicon was developed and tested.The measured quiescent power dissipation of the integrated CCOcircuit is 1.9 mW to 5.5 mW from a supply of 2–;3 V, anda typical phase noise varies from −82 to −86 dBc/Hz at 100 kHz offset. [ABSTRACT FROM AUTHOR]