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A stacked transconductor is used in the negative-resistance cell of a class-C oscillator to enable operation under a supply voltage twice as large as the nominal one for the core devices of an ultrascaled CMOS technology. This results in an increase of the maximum amplitude of oscillation by a factor two without compromising the reliability of the circuit. Consequently, the phase noise is reduced. Proof-of-concept prototypes implemented in a 22nm FD-SOI technology to assess the effectiveness of the proposed technique show a state-of-the-art phase noise of -126 dBc/Hz at 1 MHz offset from the 5.2 GHz carrier. The tuning range is 16.6%; the power consumption is 33.8 mW.