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COVID-19 has been devastating across the globe, forcing profound changes in most human interactions. Through an informal survey of numerous educators worldwide, we explore some of the disease's effects on the education community and how the online delivery of educational materials can meet these challenges.

The Computer Society’s role in the advancement of computing is increasingly important in all areas of our lives. By promoting efficiencies, accessibility, environmental responsibility, innovations, and safety, CS members and volunteers continuously contribute to a bright global future. Also, the CS faces a number of serious challenges, and looks to members to help us implement changes and pave the way for a strong future.

Over the last two years, nine IEEE Computer Society tech leaders collaborated to identify important industry advances that promise to change the world by 2022. The 23 technologies provide new insights into the emergence of "seamless intelligence."

Recent evidence suggests that adult neural stem/progenitor cells (ANSCs) secrete autocrine/paracrine factors and that these intrinsic factors are involved in the maintenance of adult neurogenesis. We identified a novel secretory molecule, stem cell-derived neural stem/progenitor cell supporting factor (SDNSF), from adult hippocampal neural stem/progenitor cells by using the signal sequence trap method. The expression of SDNSF in adult central nervous system was localized to hippocampus including dentate gyrus, where the neurogenesis persists throughout life. In induced neurogenesis status seen in ischemically treated hippocampus, the expression of SDNSF was up-regulated. As functional aspects, SDNSF protein provided a dose-dependent survival effect for ANSC following basic fibroblast growth factor 2 (FGF-2) withdrawal. ANSCs treated by SDNSF also retain self-renewal potential and multipotency in the absence of FGF-2. However, SDNSF did not have mitogenic activity, nor was it a cofactor that promoted the mitogenic effects of FGF-2. These data suggested an important role of SDNSF as an autocrine/paracrine factor in maintaining stem cell potential and lifelong neurogenesis in adult central nervous system.

Effective use of cache memory is getting more important with increasing gap between the processor speed and memory access speed. Also, use of multigrain parallelism is getting more important to improve effective performance beyond the limitation of loop iteration level parallelism. Considering these factors, this paper proposes a coarse grain task static scheduling scheme considering cache optimization. The proposed scheme schedules coarse grain tasks to threads so that shared data among coarse grain tasks can be passed via cache after task and data decomposition considering cache size at compile time. It is implemented on OSCAR Fortran multigrain parallelizing compiler and evaluated on Sun Ultra80 four-processor SMP workstation using Swim and Tomcatv from the SPEC fp 95. As the results, the proposed scheme gives us 4.56 times speedup for Swim and 2.37 times on 4 processors for Tomcatv respectively against the Sun Forte HPC Ver. 6 update 1 loop parallelizing compiler.

It is generally accepted that the direct connection from the motor cortex to spinal motor neurons is responsible for dexterous hand movements in primates. However, the role of the 'phylogenetically older' indirect pathways from the motor cortex to motor neurons, mediated by spinal interneurons, remains elusive. Here we used a novel double-infection technique to interrupt the transmission through the propriospinal neurons (PNs), which act as a relay of the indirect pathway in macaque monkeys (Macaca fuscata and Macaca mulatta). The PNs were double infected by injection of a highly efficient retrograde gene-transfer vector into their target area and subsequent injection of adeno-associated viral vector at the location of cell somata. This method enabled reversible expression of green fluorescent protein (GFP)-tagged tetanus neurotoxin, thereby permitting the selective and temporal blockade of the motor cortex–PN–motor neuron pathway. This treatment impaired reach and grasp movements, revealing a critical role for the PN-mediated pathway in the control of hand dexterity. Anti-GFP immunohistochemistry visualized the cell bodies and axonal trajectories of the blocked PNs, which confirmed their anatomical connection to motor neurons. This pathway-selective and reversible technique for blocking neural transmission does not depend on cell-specific promoters or transgenic techniques, and is a new and powerful tool for functional dissection in system-level neuroscience studies.

The superficial layer of the superior colliculus (sSC) receives visual inputs via two different pathways: from the retina and the primary visual cortex. However, the functional significance of each input for the operation of the sSC circuit remains to be identified. As a first step toward understanding the functional role of each of these inputs, we developed an optogenetic method to specifically suppress the synaptic transmission in the retino-tectal pathway. We introduced enhanced halorhodopsin (eNpHR), a yellow light-sensitive, membrane-targeting chloride pump, into mouse retinal ganglion cells (RGCs) by intravitreously injecting an adeno-associated virus serotype-2 vector carrying the CMV-eNpHR-EYFP construct. Several weeks after the injection, whole-cell recordings made from sSC neurons in slice preparations revealed that yellow laser illumination of the eNpHR-expressing retino-tectal axons, putatively synapsing onto the recorded cells, effectively inhibited EPSCs evoked by electrical stimulation of the optic nerve layer. We also showed that sSC spike activities elicited by visual stimulation were significantly reduced by laser illumination of the sSC in anesthetized mice. These results indicate that photo-activation of eNpHR expressed in RGC axons enables selective blockade of retino-tectal synaptic transmission. The method established here can most likely be applied to a variety of brain regions for studying the function of individual inputs to these regions.

This paper proposes a fast AND/OR tree search algorithm using a multiple-paths concurrent search method. Conventional heuristic AND/OR tree search algorithms expand nodes in only a descending order of heuristic evaluation values. However, since the evaluation values are heuristic, a solution node group sometimes includes nodes with lower evaluation values.The tree which has a solution node group including nodes with lower evaluation values requires a long time to be solved by the conventional algorithms.The proposed algorithm allows us to search paths including nodes with lower evaluation values and paths including nodes with higher evaluation values concurrently.For searching various paths concurrently, the proposed algorithm uses pseudo-threads and a pseudo-thread scheduler managed by a user program with low overhead compared with the OS thread management.The pseudo-thread scheduler can weight the amount of search on each path and schedule the pseudo-threads.The proposed algorithm can solve trees which have solutions including nodes with lower evaluation values also quickly.For performance evaluation, the proposed algorithm was applied to a tsume-shogi (Japanese chess problem) solver as a typical AND/OR tree search problem.In tsume-shogi, players can reuse captured pieces.Performance evaluation results on 385 problems show that the proposed algorithm is 1.67 times faster on the average than the previous algorithm df-pn.

A parallelism analysis integrated system (PARIS) with an MIMD multiprocessor scheme has been developed to analyze a simulation program which can execute anomaly effect prediction in nuclear power plants and to make the simulation program for parallel processing. The PARIS system analyzes task parallelism and processing time of each task when a user divides a program developed for a single processor into many tasks that are the elementary assignment units. Next, this system assigns tasks to processors using the static scheduling algorithm CP/MISF to minimize the overall processing time, and makes a parallel execution program which can be executed with a tightly coupled multiprocessor.The PARIS system was assessed by nuclear power plant analyzer code (NUPAC-1) consisting of a reactor coolant system model, a steam generator model and so forth. The results showed that processing time of NUPAC-1 with 7 processors was 3.5 times as fast as with a single processor, and fast running capability was 4.8 times as fast as the real physical time even in accident analyses such as small LOCA. Furthermore, the results showed the PARIS system with the MIMD multiprocessor scheme on the tightly coupled multiprocessor to be efficient for realizing the predictive simulator.

The wide use of multiprocessor system has been making automatic parallelizing compilers more important. To improve the performance of multiprocessor system more by compiler, multigrain parallelization is important. In multigrain parallelization, coarse grain task parallelism among loops and subroutines and near fine grain parallelism among statements are used in addition to the traditional loop parallelism. In addition, locality optimization to use cache effectively is also important for the performance improvement. This paper describes inter-array padding to minimize cache conflict misses among macro-tasks with data localization scheme which decomposes loops sharing the same arrays to fit cache size and executes the decomposed loops consecutively on the same processor. In the performance evaluation on Sun Ultra 80(4pe), OSCAR compiler on which the proposed scheme is implemented gave us 2.5 times speedup against the maximum performance of Sun Forte compiler automatic loop parallelization at the average of SPEC CFP95 tomcatv, swim hydro2d and turb3d programs. Also, OSCAR compiler showed 2.1 times speedup on IBM RS/6000 44p-270(4pe) against XLF compiler.

A parallel-processing scheme is described for robot-arm control computation on any number of parallel processors. The scheme employs two multiprocessor scheduling algorithms called, respectively, depth first/implicit heuristic search (DF/IHS) and critical path/most immediate successors first (CP/MISF); these were recently developed by the authors. The scheme is applied to the parallel processing of dynamic control computation for the Stanford manipulator. In particular, the proposed algorithms are applied to the computation of the Newton-Euler equations of motion for the Stanford manipulator and implemented on a multimicroprocessor system. The test result was so successful that the use of six processor pairs in parallel could attain the processing time of 5.37 ms. It is also shown that the proposed parallel-processing scheme is applicable to an arbitrary number of processors.

本論文では, ロボット制御計算のための実用的かつ汎用的な並列処理手法を提案する.提案する並列処理手法は, 高価なミニあるいはスーパーミニコンピュータの代わりに, 複数の安価なマイクロプロセッサを用いることにより, 冗長自由度を有する, あるいは有しないロボット・アームのカイネマティック制御/ダイナミック制御のための複雑な計算をリアルタイムで処理することを可能とする.また, これは同時にロボットコントローラの価格性能比・応答性・可搬性の向上等種々のメリットをもたらす.このようなメリットを十分に生かすためには, 効果的な並列処理手法の開発が非常に重要となる.ただしここで並列処理手法とは, 制御計算をどのように小さな単位 (タスク) に分割し, それらのタスクをどのようにプロセッサ上にスケージュルすべきかという方法を定義するものである.しかし, ロボット制御並列計算で要求されるスケジューリングは, 強NPハードと呼ばれるきわめて難しい最適化問題のひとつである, このため従来提案されている並列処理手法では, このスケジューリング問題を非常に簡略化しなければ解くことができず, 最小の並列処理時間を得ることができなかった.これに対して本並列処理手法は, 我々が新しく開発したマルチプロセッサ・スケジューリング・アルゴリズムDFIIHS (Depth First/Implicit Heuristicsearch) を用いることにより, 上記の非常に難しいスケジューリング問題を克服した.すなわちそれは, 任意のハードウエア構成 (プロセッサ数, プロセッサ結合方式等) のMIMDマルチプロセッサ上で, 種々のロボットに対する任意の制御アルゴリズムを, 最小時間で並列処理することを可能とする優れた手法である.

International audience; Xen is one of the most popular virtualization platforms nowadays, which has been broadly used by the industry. Credit scheduler, the default scheduler of Xen, was initially designed for serial jobs, which achieves good performance overall for serial jobs. Unfortunately, the parallel jobs are likely to co-exist with serial jobs in the same host in practice, the resource contention between virtual machines results in severe performance degradation of the parallel jobs. In this paper, we propose vGrouper, a progressive solution to enhance the performance of the parallel jobs. The vGrouper focuses on synchronizing the execution time of the parallel nodes in order to achieve the best performance of the parallel job. Moreover, the vGrouper guarantees that the parallel job nodes are able to run concurrently on pCPUs for the entire time slice, which maximizes the efficiency of communication between parallel nodes. A prototype of vGrouper is implemented, the experimental results demonstrate that the performance of the parallel job and resource utilization in Xen have been significantly improved.

International audience; Wireless local area network (WLAN) based indoor localization is expanding its fast-paced adoption to facilitate a variety of indoor location-based services (ILBS). Unfortunately, the performance of current WLAN localization systems relying on fixed access points (APs) deployment is constrained by the spatial localizability variance (SLV) problem that different locations may exhibit significantly distinct localization resolution. Prior approaches tackle this problem through nomadic APs with favorable mobility to dynamically adjust the network topology. However, the lack of prior knowledge of nomadic AP’s position has been a challenge for location distinction and will lead to prohibitive performance degradation. In this paper, we propose and develop CNLoc, a novel CSI-based (Channel State Information) indoor WLAN localization framework to overcome the location uncertainty of nomadic APs. Our implementation and evaluation show that CNLoc can improve the accuracy with unknown location information of nomadic APs. We also discuss some open issues and new possibilities in future nomadic AP based indoor localization.

International audience; The performance issue of HDFS has always been a great concern due to its widely adoption in both production and research environments. However, a fine-grained performance analysis tool is missing to effectively identify the bottlenecks as well as to provide useful guidance for performance optimization. In this paper, we propose a fine-grained performance bottleneck analysis tool, which extends HTrace with fine-grained instrumentation points that are missing in Hadoop official distribution. In addition, we propose an effective trace merging method that improves the understandability of our analysis. We analyze the performance of HDFS under different kinds of workloads and get undiscovered insights.

International audience; In HPC systems, rich metadata are defined to describe rich information about data files, like the executions that lead to the data files, the environment variables, and the parameters of all executions, etc. Recent studies have shown the feasibility of using property graph to model rich metadata and utilizing graph traversal to query rich metadata stored in the property graph. We propose to utilize GPU to process the rich metadata graphs. There are generally two challenges to utilize GPU for metadata graph query. First, there is no proper data representation for the metadata graph on GPU yet. Second, there is no optimization techniques specifically for metadata graph traversal on GPU neither. In order to tackle these challenges, we propose GRAM, a GPU-based property graph traversal and query framework. GRAM uses GPU to express metadata graph in Compressed Sparse Row (CSR) format, and uses Structure of Arrays (SoA) layout to store properties. In addition, we propose two new optimizations, parallel filtering and basic operations merging, to accelerate the metadata graph traversal. Our evaluation results show that GRAM can be effectively applied to user scenarios in HPC systems, and the performance of metadata management is greatly improved.

International audience; The training process of a neural network is the most time-consuming procedure before being deployed to applications. In this paper, we investigate the loss trend of the training data during the training process. We find that given a fixed set of hyper-parameters, pruning specific types of training data can reduce the time consumption of the training process while maintaining the accuracy of the neural network. We developed a data fine-pruning approach, which can monitor and analyse the loss trend of training instances at real-time, and based on the analysis results, temporarily pruned specific instances during the training process basing on the analysis. Furthermore, we formulate the time consumption reduced by applying our data fine-pruning approach. Extensive experiments with different neural networks are conducted to verify the effectiveness of our method. The experimental results show that applying the data fine-pruning approach can reduce the training time by around 14.29% while maintaining the accuracy of the neural network.

International audience; Dijkstra algorithm is widely used in a lot of common network routing protocols. We consider the problem of quality of service (QoS) and the Security features of the network routing area using software defined networks (SDN). The SDN framework enables an efficient decoupled implementation of dynamic routing protocols which could aware the communication network status. In this work we consider the varying delay status of the communication network along with other network security parameters. The routing problem is formulated as a multi-constrained shortest path problem. A new improved Dijkstra algorithm is presented named as QS-Dijkstra. The implement and experiment show that QS-Dijkstra algorithm is able to minimize traffic routing through vulnerable links while satisfying the QoS constraints of the network.

International audience; Resilience/fault-tolerance has become a key challenge for large-scale parallel systems. To ensure reliability of high performance computing systems, various kinds of techniques have been proposed, such as hardware-level fault-tolerance, checkpointing, replication, algorithm-base fault-tolerance, etc. There are also many software systems to monitor and handle system-failures, e.g. management and job-scheduling system of HPC systems. To evaluate the effectiveness of these systems, it is necessary to provide some kind of tool to inject failures in a HPC system. This paper proposes HPC-SFI, a system-level fault injection tool for HPC systems. Basically, HPC-SFI can generate three kinds of system-failures in a HPC system including in-node faults, failure in the interconnection network and failure of storage/parallel-file system. In addition, HPC-SFI can inject system-faults in pseudo-random model according to pre-defined parameters and probabilities. Preliminary experimental results demonstrate effectiveness of the tool.