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This brief presents a second-order discrete-time (DT) modified feed-forward (FF) delta-sigma modulator. To reduce the attenuation of the quantizer’s input signal due to switched-capacitor (SC) passive summing, the proposed modulator eliminates the internal FF path and reduces the number of input signals of the adder. A 4-bit asynchronous successive-approximation-register (SAR) analog-to-digital converter (ADC) incorporated with a passive adder is used to reduce power consumption and area. To allow the conversion delay of the SAR ADC, a delayed feedback is adopted. The prototype ADC is fabricated in a $0.11~\mu \text{m}$ CMOS process using four metal layers with an active die area of 0.165mm2. It achieves a dynamic range (DR) of 96.3 dB and a peak signal-to-noise and distortion ratio (SNDR) of 93.9 dB in a 2 kHz signal bandwidth while consuming $62.43~\mu \text{W}$ from a 1.8V/1.65V power supply, corresponding to a Schreier figure-of-merit (FOM) of 171dB.

This brief presents an ultra-low-power two-channel 12b 140 MS/s 28-nm CMOS analog-to-digital converter (ADC) for use in next-generation mobile communications systems. The proposed ADC employs a two-stage pipelined successive-approximation register (SAR) ADC architecture, where the SAR ADC at each stage determines 5b and 8b, respectively. In the first-stage 5b SAR ADC, the switching power consumption is significantly reduced due to the switching operation by only a separate digital-to-analog converter (DAC) with a small unit capacitance, which generates the comparator decision threshold. When this setup is applied to an actual system, the reference voltage driver of the system is less burdened. Furthermore, the SAR ADC employs a custom-encapsulated capacitor to improve the limited linearity of a DAC caused by parasitic capacitance. A residue amplifier employs an ultra-low power ring amplifier structure. The amplifier is shared by each channel to reduce not only the power consumption and die area but also channel mismatches. The prototype ADC in a 28-nm CMOS process demonstrates a measured differential non-linearity and integral non-linearity within 1.50 LSB and 2.85 LSB at 12b, respectively, with a maximum signal-to-noise-and-distortion ratio and a spurious-free dynamic range of 58.0 dB and 73.7 dB at 140 MS/s, respectively. The ADC occupies an active die area of 0.202 mm2 and consumes 1.1 mW at a 0.8-V supply voltage, corresponding to a figure of merit of 12.1 fJ/conversion-step.

A 12 b 50 MS/s successive-approximation register (SAR) ADC with a highly linear C-R hybrid DAC is presented. The proposed DAC significantly reduces the required total number of unit capacitors by processing the upper bits based on a binary-weighted capacitor array and the remaining lower bits based on reference segment voltages, which are obtained from a simple resistor string. The reduced number of unit capacitors enables the use of larger unit capacitance, resulting in improved matching accuracy. In the C-R hybrid DAC, an input range scaling technique, which matches a full-scale input range to the reference voltage range, implements the binary-weighted SAR operation without additional capacitors and reference voltages. The DAC linearity is improved considerably through the process-insensitive capacitor-array layout, which cancels out oxide-gradient errors. The prototype ADC in a 0.18 μm CMOS process demonstrates measured differential and integral non-linearities within 0.71 LSB and 0.85 LSB at 12 b, respectively, with a maximum signal-to-noise-and-distortion ratio and a spurious-free dynamic range of 64.3 and 74.7 dB at 50 MS/s, respectively. The ADC occupies an active die area of 0.17 mm2 and consumes 2.63 mA with a 1.8 V supply voltage.

In this study, we used a Ni/W/Ni-layered structure to provide low-resistive ohmic contacts with good thermal stability for both n-type and p-type 4H-SiC. As reference, we used Ni and Ni/Ti/Ni as control groups with specific contact resistivities, and we verified the thermal stability of the structures by specific contact resistivity measurements and thermal duration tests. We found that for both n-type and p-type semiconductors, Ni/W/Ni is superior in terms of thermal stability and specific contact resistivity. Using XRD, we also analyzed the components involved in ohmic contact and thermal stability tests.

A second-order single-bit delta-sigma analog-to-digital converter (ADC) is presented in this paper. An op-amp bias sharing technique is used to reduce the power consumption and active area of the ADC. It achieves 77.5 dB dynamic range over 1 kHz signal bandwidth with an oversampling ratio of 512. The total power consumption of the proposed ADC is 27.1 mW from a 1.0 V power supply. The prototype chip occupies 0.16 ㎟ using a 0.13 mm CMOS technology.

Continuous-rate all-digital reference-less clock and data recovery (CDR) circuit that utilises a sub-harmonic extraction scheme for wide-range frequency detection is presented. In the proposed CDR, the capture range of the frequency locked loop (FLL) is extended to the tuning range of digital controlled oscillator, thanks to the subharmonic extraction scheme. The frequency errors of FLL in lock state are within the tracking range of CDR loop. The prototype reference-less all-digital CDR, fabricated using a 40 nm CMOS technology, successfully detects 8–10 Gbit/s PRBS 231 − 1 data and produces the recovered clock. The CDR consumes 29 mW from a supply voltage of 1 V for 10 Gbit/s input data. The measured RMS jitter of the recovered clock is 2.24 ps.

This study presents a high-efficiency low-noise pulse-width modulation (PWM) DC–DC buck converter based on multi-partition switching for mobile system-on-a-chip applications. A multi-partition switching technique is employed for the control of large current driving switches to minimise the switching noise. In addition, a PWM control with a switching frequency of 2 MHz is applied for the driving of output stage with a heavy load to optimise the power efficiency. The prototype DC–DC buck converter with an active die area of 0.28 mm2 was implemented using a 0.18 µm bipolar-CMOS–DMOS (BCD) process. The peak power efficiency is 93%, while supplying an output current of 200 mA and an output voltage of 1.8 V.

This paper proposes a low-power rangescaled 14b 30 MS/s pipeline-SAR composite ADC for high-performance CIS applications. The SAR ADC is employed in the first stage to alleviate a samplingtime mismatch as observed in the conventional SHA-free architecture. A range-scaling technique processes a wide input range of 3.0VP-P without thick-gate-oxide transistors under a 1.8 V supply voltage. The firstand second-stage MDACs share a single amplifier to reduce power consumption and chip area. Moreover, two separate reference voltage drivers for the firststage SAR ADC and the remaining pipeline stages reduce a reference voltage disturbance caused by the high-speed switching noise from the SAR ADC. The measured DNL and INL of the prototype ADC in a 0.18 μm CMOS are within 0.88 LSB and 3.28 LSB, respectively. The ADC shows a maximum SNDR of 65.4 dB and SFDR of 78.9 dB at 30 MS/s, respectively. The ADC with an active die area of 1.43 mm 2 consumes 20.5 mW at a 1.8 V supply voltage and 30 MS/s, which corresponds to a figure-of-merit (FOM) of 0.45 pJ/conversion-step.

Moving target has a non-coherent phase characteristic regardless of micro-Doppler effect caused by body motion, because the movement of the target changes the beat-frequency and its phase. A phase compensation method to remove the phase variations caused by movement is proposed. Using the proposed phase compensation method, it is possible to classify targets as pedestrians or automobiles based on the phase variance because pedestrians and automobiles have non-coherent and coherent phases, respectively. Through applying experimental data, the possibility of target classification is shown.

This work proposes a low-noise four-stage pipeline ADC operating at 14 b 50 MS/s and 10 b 70 MS/s for high-end CIS applications. In the 10 b 70 MS/s mode, the last-stage MDAC and flash ADC are turned off rather than the first-stage MDAC and flash ADC for the same input-referred noise in both modes. The proposed ADC shares a single amplifier for the first- and second-stage MDACs to reduce power consumption and chip area. The amplifier thermal noise of the SHA and MDACs is minimized by adjusting the trans-conductance of input and current-source transistors while two separate reference voltage drivers for the MDACs and the flash ADCs reduce the switching noise. The prototype ADC in a 0.13 μm CMOS technology providing 0.35 μm thick-gate-oxide transistors shows the measured DNL and INL within 0.79 and 2.54 LSB in the 14 b mode, and 0.53 and 0.44 LSB in the 10 b mode, respectively. The ADC shows the maximum SNDR and SFDR of 68.5 and 86.7 dB in the 14 b 50 MS/s mode, and the SNDR and SFDR of 60.5 and 77.8 dB for the 10 b 70 MS/s mode, respectively. The ADC with the measured input-referred noise of 1.20 LSBrms/14 b consumes 192.9 mW at the 14 b 50 MS/s, and 184.9 mW in the 10 b 70 MS/s mode with 3.3/1.2 V dual supplies.

This work proposes a 12b 100 MS/s 0.11 m CMOS three-step hybrid pipeline ADC for high- speed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dual- channel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a 0.11 m CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of 1.34 mm 2 and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.

A 1.1 V 81.8 dB delta-sigma analog-to-digital converter (ADC) is presented. The split time integration technique for implementing multi-bit digital-to-analog converter (DAC) without using DEM has been developed and used. In order to reduce power consumption and area, a successive approximation register (SAR) ADC is employed to function as both multi-bit quantizer and summing adder without using an additional amplifier. The proposed deltasigma modulator operates at a 640 kHz clock rate and dissipates 850 W with a 1.1 V supply. It achieves 81.8 dB dynamic range (DR), 76.8 dB signal-to-noise and distortion ratio (SNDR) over a 5 kHz signal bandwidth. The core area is 235 m 2 in a 45-nm CMOS technology.

This brief presents a 10-bit 100-MS/s 1.2-V dual-channel pipelined CMOS analog-to-digital converter (ADC). The nine dual-channel pipelined stages share the operational amplifiers (op-amps) to optimize power and area. The proposed dynamic memory effect cancellation technique reduces the cross coupling caused by the residual charge in the op-amp sharing topology. The op-amp gain requirement of the dual-channel sample-and-hold circuit is also relaxed by the proposed memory effect cancellation technique. The prototype ADC achieves a peak signal-to-noise and distortion ratio of 56 dB for a 1-MHz input signal and a peak cross-coupling ratio of 67.4 dB at 100 MS/s while consuming 16.2 mW/channel from a 1.2-V supply. The prototype ADC occupies 1.96 mm2 using a 0.13-μm CMOS technology.

— A 2.5 V feed-forward second-order delta-sigma modulator for audio application is presented. A 9-level quantizer with a tree-structured dynamic element matching (DEM) was employed to improve the linearity by shaping the distortion resulted from the capacitor mismatch of the feedback digital-to-analog converter (DAC). A chopper stabilization technique (CHS) is used to reduce the flicker noise in the first integrator. The prototype delta-sigma analog-to-digital converter (ADC) implemented in a 65 nm 1P8M CMOS process occupies 0.747 mm 2 and achieves 109.1 dB dynamic range (DR), 85.4 dB signal-to-noise ratio (SNR) in a 24 kHz audio signal bandwidth, while consuming 14.75 mW from a 2.5 V supply. Index Terms —Delta-sigma modulator, feed-forward, dynamic element matching, chopper stabilization I. I NTRODUCTION Recent advances of CMOS technology have enabled the high quality signal processing in the multi-media and communication systems and have resulted in a great demand for the high resolution analog-to-digital converters (ADCs). Among various ADC architectures, the delta-sigma ADC offers high dynamic range by using oversampling and noise shaping properties. Moreover, as it requires only simple and relatively high-tolerance analog components with fast and complex digital signal processing to achieve high resolution, it is very well-suited for the digital CMOS process. The theoretical signal-to-quantization noise ratio (SQNR) of the delta-sigma ADC is given by Eq. (1)

A 12b 2 MS/s cyclic ADC processing 3.3 Vpp single-ended rail-to-rail input signals is presented. The proposed ADC demonstrates an offset voltage less than 1 ㎷ without well-known calibration and trimming techniques although power supplies are directly employed as voltage references. The SHA-free input sampling scheme and the two-stage switched op-amp discussed in this work reduce power dissipation, while the comparators based on capacitor-divided voltage references show a matched full-scale performance between two flash sub ADCs. The prototype ADC in a 0.18 ㎛ 1P6M CMOS demonstrates the effective number of bits of 11.48 for a 100 ㎑ fullscale input at 2 MS/s. The ADC with an active die area of 0.12 ㎟ consumes 3.6 ㎽ at 2 MS/s and 3.3 V (analog)/1.8 V (digital).

This paper describes a 12-b 120-MS/s dual-channel pipeline analog-to-digital converter (ADC) for high-speed video signal processing. A simple digital midcode calibration technique is proposed to eliminate an offset mismatch between two channels. The proposed sample-and-hold-amplifier-free architecture with correlated input sampling networks enables wideband signal sampling while effectively reducing a gain mismatch between channels. The prototype ADC implemented in a 0.13-?m CMOS technology achieves a peak signal-to-noise-and-distortion ratio of 61.1 dB and a peak spurious-free dynamic range of 74.7 dB for input frequencies up to 60 MHz at 120 MS/s. The measured differential and integral nonlinearities are within ±0.30 LSB and ±0.95 LSB, respectively. The ADC occupies an active die area of 0.56 mm2 and consumes 51.6 mW at a 1.2 V power supply.

An ultra-low-voltage CMOS two-stage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted low-voltage circuit technique achieves high-accuracy high-speed clocking without the use of clock boosting or bootstrapping. A resistor-based input sampling branch demonstrates high linearity and inherent low-voltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a two-channel ADC architecture. The prototype ADC, fabricated in a 0.18 /spl mu/m CMOS process, achieves 77-dB SFDR at 0.9 V and 5MSPS (30 MHz clocking) after calibration. The measured SNR, SNDR, DNL, and INL at 80 kHz input are 50 dB, 50 dB, 0.6 LSB, and 1.4 LSB, respectively. The total power consumption is 12 mW, and the active die area is 1.4 mm/sup 2/.

The design of an ultra-low-voltage multistage (two-stage algorithmic) analog-to-digital converter (ADC) employing the opamp-reset switching technique is described. A highly linear input sampling circuit accommodates truly low-voltage sampling from external input signal source. A radix-based digital calibration technique is used to compensate for component mismatches and reduced opamp gain under low supply voltage. The radix-based scheme is based on a half-reference multiplying digital-to-analog converter structure, where the error sources seen by both the reference and input signal paths are made identical for a given stage. The prototype ADC was fabricated in a 0.18-/spl mu/m CMOS process. The prototype integrated circuit dissipates 9 mW at 0.9-V supply with an input signal range of 0.9 V/sub p-p/ differential. The calibration of the ADC improves the signal-to-noise-plus-distortion ratio from 40 to 55 dB and the spurious-free dynamic range from 47 to 75 dB.

A switched-capacitor single-stage sigma-delta ADC with a fifth-order modulator is proposed. The proposed sigma-delta ADC employs feed-forward architecture with oversampling ratio (OSR) of 8. The modulator input signal range is extended beyond the full scale of the quantizer with proper coefficients scaling and internal DAC reference scaling. A 19-level quantizer with data weighted averaging dynamic element matching (DWA DEM) technique is employed to improve the linearity of a multi-bit DAC. The prototype ADC fabricated in a 0.13-µm CMOS technology achieves 63.7 dB SNDR with 1 MHz input signal over 6.25 MHz signal bandwidth while consuming 52.5 mW with the clock frequency of 100 MHz.

A 12b 10MS/s pipelined ADC using reference scaling achieves 62 dB SNDR and 72 dB SFDR for a 1MHz input. The prototype IC fabricated in a 0.35mum CMOS process employs interstage amplifiers with 45dB open-loop gain and consumes 19mW from a 2.4V supply

An ultra low-voltage CMOS two-stage algorithm ADC incorporating background digital calibration is presented. The adopted low-voltage circuit technique achieves high-accuracy high-speed clocking without the use of clock boosting or bootstrapping. A resistor-based input sampling branch demonstrates high linearity and inherent low-voltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a two-channel ADC architecture. The prototype ADC, fabricated in a 0.18 /spl mu/m CMOS process, achieves 81 dB SFDR at 0.9V and 2MSPS (12MHz clock) after calibration. The ADC operates up to 5MSPS (30MHz clock) with 4dB degradation. The total power consumption is 12mW, and the active die area is 1.4 mm/sup 2/.

An improved algorithmic ADC clocking scheme is presented. Using an optimized clock generator, a significant improvement in conversion speed is achieved in the converter. This proposed optimized clock generator removes the wasted time which exists during all conversion cycles except for the first one. This technique can improve the conversion speed up to 82% compared to conventional algorithmic ADCs. Alternatively, static power consumption can also be reduced for a given conversion speed. An algorithmic ADC using the new clocking scheme is validated using MATLAB behavioral simulations.

A 12b 50 MS/s 0.18 µm CMOS ADC with a highly linear variable gain amplifier (VGA) for medical ultrasound and CCD image sensor applications is presented. The proposed four-step pipeline ADC optimises power and chip area at target specifications while the front-end VGA, based on a conventional approximated log function, employs a merged capacitor switching scheme to improve the VGA gain linearity. The proposed input VGA shows a linearity error less than 0.013 dB in a gain range from −3 to 0 dB by a 0.2 dB step. The measured prototype ADC with an active die area of 1.09 mm2 shows a maximum SNDR and SFDR of 62.6 and 73.1 dB, respectively, and consumes 28.1 mW at 1.8 V and 50 MS/s.