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In this paper, we investigated the electrical properties of the Metal-oxide-semiconductor gate stack of Ti/Al2O3/InP under different annealing conditions. A minimum interface trap density of 3×1011cm-2eV-1 is obtained without postmetallization annealing treatment. Additionally, utilizing Ti/Al2O3/InP MOS gate stack, we fabricated ultra-thin body buried In0.35Ga0.65As channel MOSFETs on Si substrates with optimized on/off trade-off. The 200nm gate length device with extremely low off-current of 0.6nA/µm, and on-off ratio of 3.3×105, is demonstrated by employing buried low indium (In0.35Ga0.65As) channel with InP barrier/spacer device structure, giving strong potential for future highperformance and low-power applications.

In this work, the impact of back gate work function on analog/RF performance of Asymmetric Junctionless Dual Material Double Gate MOSFET with high K gate Stack (AJDMDG Stack MOSFET) has been studied. The impact of back gate work function on analog/RF parameters like drain current (ID), transconductance (gm), transconductance generation factor (TGF), intrinsic gain, output resistance (rout), cut-off frequency, maximum frequency of oscillation (fmax) etc. have been studied through TCAD device simulator. The results reveal that an improvement in analog/RF performance has been achieved by choosing a low value work function of the back gate.

We report Negative Capacitance nFETs with a ~ 1 nm effective oxide thickness (EOT) gate stack. Experimental measurements show a clear steepening of the slope of the ID-VG characteristic in the weak inversion regime, indicating that a capacitance matching takes place there. This leads to non-linear behavior of the current in the log scale, which is not observed in conventional devices. Such steepening in the weak inversion regime leads to a significant increase in the achievable current at a constant VDD. At LG = 50 nm, our transistors show a larger than 2X increase in the ON current.

For the development of reliable vertical GaN transistors, a detailed analysis of the robustness of the gate stack is necessary, as a function of the process parameters and material properties. To this aim, we report a detailed analysis of breakdown performance of planar GaN-on-Si MOS capacitors. The analysis is carried out on capacitors processed on different GaN bulk doping (6E18 Si/cc, 6E17 Si/cc and 2.5E18 Mg/cc, p-type), different structures (planar, trench-like) and different geometries (area, perimeter and shape). We demonstrate that (i) capacitors on p-GaN have better breakdown performance; (ii) the presence of a trench structure significantly reduces breakdown capabilities; (iii) breakdown voltage is dependent on area, with a decreasing robustness for increasing dimensions; (iv) breakdown voltage is independent of shape (rectangular, circular). TCAD simulations, in agreement with the measurements, illustrate the electric field distribution near breakdown and clarify the results obtained experimentally., ["European Union (EU)" & "Horizon 2020"]["Euratom" & Euratom research & training programme 2014-2018"][Research for GaN technologies, devices, packages and applications to address the challenges of the future GaN roadmap][UltimateGaN][826392]

In this paper, analog/radio frequency (RF) electrical characteristics of triple material gate stackgraded channel double gate-Junctionless (TMGS-GCDGJL) strained-Si (s-Si) MOSFET with fixed charge density is analyzed with the help of Sentaurus TCAD. By varying the various device parameters, the analog/RF performance of the proposed TMGS-GCDG-JL s-Si MOSFET is evaluated in terms of transconductance-generationfactor (TGF), early voltage, voltage gain, unity-powergain frequency ( f max ), unity-current-gain frequency ( f t ), and gain-transconductance frequency product (GTFP). The results confirm that the proposed TMGS-GCDGJL s-Si MOSFET has superior analog/RF performance compared to gate stack-graded channel double gatejunctionless (GS-GCDG-JL) s-Si device. However, the proposed MOSFET has less transconductance and less output conductance when compared with the GS-GCDGJL s-Si device in above threshold region, and reverse trend follows in sub-threshold region.

In this paper, for the first time, we have experimentally demonstrated enhancement mode (e-mode) AlGaN/GaN high-electron-mobility transistor (HEMT) operation by integrating p-type high- $\kappa {\mathrm {Al}}_{x}{\mathrm {Ti}}_{1-x}$ O based gate stack. Concentration of Al in Al-Ti-O system was found to be a tuning parameter for the threshold voltage of GaN HEMTs. The high- $\kappa $ properties of ${\mathrm {Al}}_{x}{\mathrm {Ti}}_{1-x}$ O as a function of Al % are studied. Superiority of AlTiO over other p-oxides such as CuO and NiO x is proven statistically. Using the high- $\kappa $ and p-type AlTiO, in conjunction with a thinner AlGaN barrier under gate, 600-V e-mode GaN HEMTs are demonstrated with superior ON-state performance ( $\text{I}_{ \mathrm{\scriptscriptstyle ON}}~\sim ~400$ mA/mm and $\text{R}_{ \mathrm{\scriptscriptstyle ON}} ={8.9}\,\,\Omega $ -mm) and gate control over channel ( $\text{I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}} = {10}^{{7}}$ , SS = 73 mV/dec, and gate leakage

Electrical properties of Y2O3/SiGe metal-oxide-semiconductor (MOS) capacitors with Al, Au, W and TiN gate electrodes have been evaluated in order to study the impact of the metal gate electrodes on Y2O3/SiGe interface properties. It is found that MOS capacitors with TiN gate electrodes can provide better Y2O3/SiGe MOS interfaces than those with Al, Au or and W gate stacks after post metallization annealing (PMA) at each optimized temperature. The physical origins of interface trap density (Dit) reduction are examined from the viewpoint of the composition and the quality of interfacial layers (ILs).

We investigate the impact of gate-stack engineering using W/ZrO2/Al2O3 on the performance of planar-type InGaAs tunneling field-effect transistors (TFETs). It is shown that 1-nm-thick capacitance equivalent thickness (CET) with low leakage current is achieved by using ZrO2 with the dielectric constant of around 40 on In0.53Ga0.47As. On the other hand, the reduction of Dit by insertion of ALD 1–5 cycle Al2O3 interfacial layers (ILs) is found to be mandatory for obtaining TFET performance enhancement. The planar-type InGaAs TFETs using the ZrO2/Al2O3 IL gate-stack with CET of 1 nm exhibit the minimum subthreshold swing (S. $\text{S}_{\min }$ ) of 55 mV/dec and ${I}_{ \mathrm{\scriptscriptstyle ON}}$ of $0.88~\mu \text{A}/\mu \text{m}$ ( ${V}_{\text {G}}$ – ${V}_{ \mathrm{\scriptscriptstyle OFF}}= \text {0.5}$ V, ${V}_{\text {D}}= \text {0.2}$ V, and ${I}_{ \mathrm{\scriptscriptstyle OFF}}= \text {10}$ pA/ $\mu \text{m}$ ). Furthermore, the ZrO2/Al2O3 IL gate-stack is applied to the optimized In0.75Ga0.25As quantum well (QW) channel TFETs. The low S. $\text{S}_{\min }$ of 50 mV/dec and high ${I}_{ \mathrm{\scriptscriptstyle ON}}$ of $1.2~\mu \text{A}/\mu \text{m}$ ( ${V}_{\text {G}}$ – ${V}_{ \mathrm{\scriptscriptstyle OFF}}= \text {0.5}$ V, ${V}_{\text {D}}= \text {0.2}$ V, ${I}_{ \mathrm{\scriptscriptstyle OFF}}= \text {10}$ pA/ $\mu \text{m}$ , and CET = 1.1 nm) are demonstrated by combing the present ZrO2-based gate-stack with the optimum In0.75Ga0.25As QW channel structure.

The main purpose of this paper is to achieve as low as possible leakage current ( $\text{I}_{\mathrm { \mathrm{\scriptscriptstyle OFF}}}$ ) to meet the requirements for ultra-low power (ULP) applications. The proposed methodology is based on studying the effect of the most effective FinFET design parameters that directly impact its leakage current. The parameters explored in this paper are the effective channel lengths $\text{L}_{\mathrm {eff}}$ , gate stacks, gate contact materials, and gate-sidewall spacers ( $\text{L}_{\mathrm {sp}}$ ). The results show that utilizing a symmetrical dual-k material for 7-nm underlap tri-gate FinFETs appreciably allows a sufficient ON current and low leakage current and hence low stand by power consumption. Specifically, the effect of spacer length $\text{L}_{\mathrm {sp}}$ and $\text{L}_{\mathrm {HK}}$ is investigated to get low leakage current keeping $\text{I}_{\mathrm { \mathrm{\scriptscriptstyle ON}}}/\text{I}_{\mathrm { \mathrm{\scriptscriptstyle OFF}}}$ as high as possible. Moreover, the effective channel length in subthreshold conduction ( $\text{L}_{\mathrm {eff}}$ ) is maintained greater than the gate length ( $\text{L}_{\mathrm {g}}$ ) and the threshold voltage ( $\text{V}_{\mathrm {th}}$ ) is adjusted by the proper metal gate work function. The performance of the proposed n- and p-FinFET devices is verified using Sentaurus TCAD simulator from Synopsys. The resulted $\text{I}_{\mathrm { \mathrm{\scriptscriptstyle OFF}}}$ is 17 pA/ $\mu $ m for n-FinFET and 14.7 pA/ $\mu \text{m}$ for p-FinFET which are the lowest leakage currents found in recent publications. The achieved $\text{I}_{\mathrm { \mathrm{\scriptscriptstyle ON}}}/\text{I}_{\mathrm { \mathrm{\scriptscriptstyle OFF}}}$ ratio for both proposed devices is found to be $12.3 \times 10^{6}$ and $11 \times 10^{6}$ , respectively, which are comparable to the published data. These parameters are obtained for an appropriate choice of $\text{L}_{\mathrm {sp}}=10$ nm and $\text{L}_{\mathrm {HK}}= 5$ nm. In addition, the short channel effects variations with $\text{L}_{\mathrm {HK}}$ have been investigated.

With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage. This led to the adoption of high-κ dielectric HfO2 in the gate stack in 2008, which remains as the material of choice to date. Here, we report HfO2-ZrO2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto Si transistors and scaled down to ~ 20 Å, the same gate oxide thickness required for high performance transistors. The overall EOT (equivalent oxide thickness) in metal-oxide-semiconductor capacitors is equivalent to ~ 6.5 Å effective SiO2 thickness, which is, counterintuitively, even smaller than the interfacial SiO2 thickness (8.0-8.5 Å) itself. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO2-based high-κ dielectric gate stacks without scavenging the interfacial SiO2, which has adverse effects on the electron transport and gate leakage current. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. Therefore, our work demonstrates that HfO2-ZrO2 multilayers with competing ferroelectric-antiferroelectric order, stabilized in the 2 nm thickness regime, provides a new path towards advanced gate oxide stacks in electronic devices beyond the conventional HfO2-based high-κ dielectrics.

We present a detailed study of the effect of gate-oxide-related defects (traps) on the small-signal radio frequency (RF) response of III-V nanowire MOSFETs and find that the effects are clearly identifiable in the measured admittance parameters and in important design parameters such as h 21 (forward current gain) and MSG (maximum stable gain). We include the identified effects in a small-signal model alongside results from previous investigations of III-V RF MOSFETs and thus provide a comprehensive physical small-signal RF model for this type of transistor, which accurately describes the measured admittance parameters and gains. We verify the physical basis of the model assumptions by calculating the oxide defect density from the measured admittances.

In this work, we discuss how the insertion of a LaSiOx layer in between an in-house IL passivation layer and the high-k has moved the III-V gate stack into the target window for future technology nodes. The insertion of this LaSiOx layer in the gate stack has reduced the Dit and Nbt below the target level of 5×1011 /eV.cm2 and 3×1010 /cm2 (target at 10 years operation: ΔVfb

In this work, the investigation of high- K gate-stack-based junctionless (JL) double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is carried out to study the high- K gate dielectric effect on six-transistor (6T)-static random-access memory (SRAM) built with JLDG-MOSFET. It is observed that the utilisation of the high- K gate dielectric in JLDG-MOSFETs improves the static noise margin (SNM) that is the stability of the cell as well as access time (AT) which reflects the delay performance of the SRAM cell. Furthermore, scaling down of L g degrades the stability. Moreover, it is also described that the enhancement in hold SNM (ΔHSNM = HSNM (K=40) -HSNM (K=3.9) ), read SNM (ΔRSNM = RSNM (K=40) -RSNM (K=3.9) ), and write SNM (ΔWSNM = WSNM (K=40) -WSNM (K=3.9) ) is restricted at lower L g without much enhancement in the improvement of read AT and write AT. Therefore, it is appropriate to consider higher channel length (~30 nm) while designing high- K gate-stacked-based JLDG-MOSFETs for the 6T-SRAM cell.

Recent demonstration of aggressively scaled HfO2-based ferroelectric field effect transistors (FE-HfO2-FETs) has illustrated a pathway to fabricate FeFETs that enjoy COMS-compatibility, low power, fast switching speed, scalability, and long retention. One potential issue of this promising technology is its limited endurance, which has been attributed to the degradation of gate stack before the fatigue of polarization in the ferroelectric HfO2 layer. Some associated work has identified charge trapping and trap generation as key villains, but a clear understanding of two aforementioned underlining mechanisms is still missing. In this letter, we initiated this letter to investigate the roles of charge trapping and trap generation in causing endurance failure of FE-HfO2 FETs.

The high performance Ge pMOSFETs have been realized with ultrathin HfO2/AlO x /GeO x /Ge gate-stacks fabricated by ozone postoxidation (OPO) and NiGe metal source/drain (S/D). It is found that OPO yields a reduction of interface traps and an improvement of dielectric strength for the HfO2/AlO x /GeO x /Ge gate-stacks. On the other hand, it is also confirmed that the NiGe metal S/D structure decreases the S/D parasitic resistance severely. As a result, the record high drive current has been realized under a comparable gate length for present Ge pMOSFET structure with the ultrathin equivalent oxide thickness HfO2/AlO x /GeO x /Ge gate-stack and the low parasitic resistance NiGe S/D.

Aluminum oxynitride (AlON) is investigated as a germanium oxide (GeO) desorption barrier layer for Ge MOSFETs. Interface and border traps in the AlON/GeO2/Ge gate-stack are discussed in detail and compared with those in the Al2O3/GeO2/Ge gate-stack via MOS and MOSFET structures. Although the interface traps remain the same for AlON and Al2O3 in the gate stacks, the AlON gate-stack exhibits a reduced border trap, which results in improved reliability over the Al2O3 gate-stack. This is supported by both the charge-trapping and low-frequency noise analyses.

This paper studied the recess-etching effects on the temperature-dependent characteristics of AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) with Al2O3/AlN gate-stack. The 12.6 nm recess-etching resulted in voltage shift of capacitance-voltage curves by 2.4 V, improved peak field-effect mobility ( $\mu _{\text {FE}})$ from 1906 to 2036 cm2/ $\text{V}\cdot \text{s}$ , and increased peak transconductance ( ${g}_{\text {max}})$ from 272 to 353 mS/mm. The temperature-dependent measu-rement from 298 to 473 K showed decrease in maximum drain current, ${g}_{\text {max}}$ , and $\mu _{\text {FE}}$ for both devices with and without recess etching, attributed to thermal electron emission and carrier depletion effects. Recess etching did not degrade the thermal stability of carrier distribution and the transport properties. Temperature-dependent $\mu _{\text {FE}}$ analysis revealed that optical phonon scattering dominated the transport mechanism of Al2O3/AlN/ AlGaN/GaN MIS-HEMTs. Optical phonon energy of 74 and 77 meV were obtained for the devices with and without recess etching, respectively.

HfAlO/Ge gate stack with Al 2 O 3 passivation layer and different Al 2 O 3 concentration in HfAlO layer has been deposited on Ge substrate by atomic layer deposition. Based on measurements from capacitance-voltage and current density-voltage curves, the evolution of the electrical properties of Ge-based MOS capacitors based on HfAlO/Al 2 O 3 /Ge gate stack has been determined as functions of precursor ratio and annealing temperature. It has been found that high annealing temperature and high Al 2 O 3 incorporation in HfAlO films can obtain improved electrical properties such as low hysteresis, low flat-band, low flat-band shift and low interface-state density. However, the oxide-charge density obviously increases with rising the annealing temperature and decreasing Al 2 O 3 incorporation in HfAlO film. By analysis and calculation, it can be noted that the samples annealed at 500 °C holds the lowest leakage current density and the change of the precursor ratio has no apparent effect in 500 °C-annealed Ge MOS capacitor. To investigate current conduction mechanism of Ge MOS capacitors employing HfAlO/Al 2 O 3 gate stacks, current density-voltage measurements have been carried out as functions of annealing temperature and precursor ratio. The involved leakage current conduction mechanisms of the as-deposited and 500 °C-annealed HfAlO/Al 2 O 3 /Ge MOS capacitors for substrate injection also have been discussed in detail.

In this paper, we propose a novel dual-metal gate-stack (DMSG) architecture with HfO2 spacer for scaling the nanowire FETs (NWFETs) to the sub-10-nm regime. We demonstrate that the electric field at the channel–drain extension interface is reduced when the inbuilt electric field arising due to a difference in the work function at the interface of the two metals in the DMSG is coupled to the nanowire through the fringing fields through the HfO2 spacer. The reduction in the electric field leads to a larger tunneling width, and therefore suppresses the lateral band-to-band-tunneling component of the gate-induced drain leakage in the DMSG NWFETs. Although the gate capacitance increases in the DMSG NWFETs due to the fringing fields, this paper demonstrates that the increase in the intrinsic delay (~1.5 times) is not very significant to degrade the circuit performance drastically. Using calibrated 3-D simulations, we show that the off-state current is reduced by more than five orders of magnitude in the DMSG NWFETs, leading to a significantly high on-state to off-state current ratio of ~106 even when the channel length is scaled to 7 nm.

The novelty of this study lies in the application of the scanning tunneling microscopy (STM), to study the electronic properties of the high-k gate stack at nanometre scale. The samples are the HfO2/SiOx and the Sc2O3/La2O3/SiOx gate stacks. Based on tunneling and energy band theory, the polycrystalline structure with grain size of ~27 nm of the high-k and the amorphous SiOx can be imaged independently at different biasing polarity. The polarity dependent STM current can therefore allow the demarcation of electronic traps in the high-k and the SiOx layer. This allows the evolution of electronic traps in each layer to be separately probed and studied under process condition change and electrical stress. By subjecting the high-k gate stack to different post-deposition annealing (PDA) temperatures, electrical weak spots and non-uniformity induced by PDA can be revealed by STM. Lateral resolved I-V characteristics extracted from leakage sites are found to exhibit either stress induced leakage current (SILC) or barrier height lowering (BHL) behaviors. STM observation of thermally induced localized low resistance path under tip injection and increase in leakage sites density in annealed gate stacks explain the reduced Weibull slope upon PDA. DOCTOR OF PHILOSOPHY (EEE)

Nanocrystal (NC) memories have attracted a lot of research attentions as a promising candidate to reduce defect-related charge loss and to overcome scaling limitation in conventional floating gate memories. Most work on metal nanocrystal (MNC) has focused primarily on the materials and fabrication issues, while the reliability aspects have been greatly ignored, such as inter-dot tunneling among NCs, the charge loss mechanisms and their performances in the degraded dielectric gate stacks which are of utmost importance for the device optimization and future scaling. This work focuses on the degradation and reliability of MNC embedded gate stacks, contributes to a deeper understanding of MNC performances in the degraded dielectric gate stacks and its charge transport behaviors, and reports extensively on the reliability characterization of both single-layer and dual-layer MNC embedded gate stacks. To enable strong gate coupling and low operating voltage, NCs are conventionally embedded in the high-κ layer. Therefore, the overall dielectric gate stack in conventional NC memories typically consists of a tunneling oxide layer and a NC-embedded high-κ layer. It is thus important to understand the performance of MNCs in the case of the individual dielectric layer degradation. Firstly, we report the influence of dielectric degradation on charging and discharging characteristics of MNCs embedded in high-/SiO2 gate stacks. It is found that the charging and discharging phenomena of the MNCs and leakage mechanism in the degraded gate stacks are strongly dependent on the lateral charge tunneling/hopping among the NCs. Our experimental results show that the localized breakdown not only affects charge holding capability of the affected NCs, but also provides a leakage path for the charges stored in the surrounding NCs. It indicates the existence of lateral charge diffusion in the MNCs. Next, the post-breakdown characteristics of the conduction path formed in the individual different dielectric layer (either SiO2 or NC-embedded Al2O3) are identified. The first layer to breakdown is determined based on the physics underlying the Coulomb charging energy in relation to thermal energy gained by electrons at low voltage and in the very low temperature regime ranging from 11K to 70K. With this approach, the average trap (defect) size in NC-embedded high-κ and SiO2 is further analyzed. It is noted that breakdown in SiO2 leads to lateral charging/discharging among NCs while in Al2O3, it leads to spontaneous breakdown of bi-layer gate stacks owing to high localized trap generation rate around the high-κ dielectric grain boundary and local electric field enhancement in the vicinity of MNCs. To further confirm the lateral charge diffusion of MNCs observed in the degraded dielectric gate stacks, the localized charge transport and lateral charge diffusion phenomena in MNCs are investigated by Kelvin Force Microscopy (KFM) characterization. The results reveal that vertical charge loss and lateral charge diffusion are two competing mechanisms and they can be identified by discharging current measurements at elevated temperatures and KFM characterization. It is found that the MNC with higher work function has a lower inter-dot charge tunneling probability, which is favorable for improved retention in memory applications. However, the vertical charge loss during the initial decay period is a trade-off and hence it could be minimized by using dual-layer (DL) MNC structure wherein electron de-trapped from one-NC layer could be “re-trapped” in the adjacent NC layer. Therefore, the DL-MNC devices with high work function MNCs are chosen to study their intrinsic charge loss mechanisms and inter-dot tunneling and inter-layer tunneling characteristics. A comparative study is performed on the DL devices with inter-layer dielectric (ILD) thickness variation. The temperature and gate-bias accelerated retention measurements and KFM approaches are used. It is found that charge loss in DL structures is mainly due to the internal electric field induced by trapped electrons which depends on the ILD thickness and MNC spacing. When the ILD thickness is comparable to MNCs spacing, the charge distribution in two-MNC layers are similar and the internal electric field induced by charges stored in the MNCs is higher. It leads to the fact that internal-electric-field assisted tunneling dominates at lower temperature. In contrast, when the ILD thickness is larger than the average MNC spacing, less charges are injected in the neighboring MNC layer, resulting in a reduction of both internal electric field and oxide trap alignment possibility with the traps inside the MNCs. Moreover, a thick ILD reduces the electron tunneling probability from one MNC-layer to another during retention. Our findings suggest that an optimized DL-MNCs embedded memory cell could be achieved by defining the ILD thickness larger than the average MNC-spacing for enhancement of retention ability in MNC embedded gate stacks. It implies the possibility of reducing MNC spacing in scaled memory devices by using DL-MNCs with controlled ILD thickness to achieve both increased memory window and prolonged retention. In summary, the dielectric degradation and fundamental reliability issues in MNC embedded gate stacks are investigated in details and comprehensive understanding of inter-dot tunneling and charge loss mechanisms in MNC embedded gate stack is achieved for optimum memory cell design with retention reliability perspective. DOCTOR OF PHILOSOPHY (EEE)

The HfO2-based ferroelectric field effect transistor (FeFET) with a metal/ferroelectric/insulator/semiconductor (MFIS) gate stack is currently being considered as a possible candidate for high-density and fast write speed non-volatile memory. Although the retention performance of the HfO2-based FeFET with a MFIS gate stack could satisfy the requirements for practical applications, its memory window (MW) and reliability with respect to endurance should be further improved. This work investigates the advantage of employing ZrO2 seed layers on the MW, retention, and endurance of the Hf0.5Zr0.5O2 (HZO)-based FeFETs with MFIS gate stacks, by using fast voltage pulse measurements. It is found that the HZO-based FeFET with a ZrO2 seed layer shows a larger initial and 10-year extrapolated MW, as well as improved endurance performance compared with the HZO-based FeFET without the ZrO2 seed layer. The results indicate that employing of a direct crystalline high-k/Si gate stack would further improve the MW and reliability of the HfO2-based FeFETs.

Several mechanisms may contribute to the degradation of GaN transistors; in this paper we discuss the main processes that limit the lifetime of GaN power devices, with focus on the following relevant aspects: (i) the degradation/breakdown induced by off-state bias; (ii) the origin of vertical leakage and breakdown; (iii) the failure of the gate stack in MIS-HEMTs and in transistors with p-type gate. The data reviewed in this paper help the reader understanding the main issues related to the development of GaN-based transistors, and give hints on possible strategies to improve device reliability. The signatures of the main deep levels in gallium nitride, which can influence the reliability of the devices, are critically reviewed and summarized.

The impact of postdeposition annealing (PDA) ambient on electrical properties of thin equivalent oxide thickness (EOT) Al2O3/GeO x /Ge gate-stacks is investigated. It is found that the surface states inside the conduction band of Ge are significantly suppressed by 40% through PDA with atomic deuterium ambient. As a result, enhancement of the effective mobility in the Ge nMOSFETs is realized in high normal field region. The electron mobility of 396 cm2/Vs is achieved at $N_{s}$ of $10^{13}$ cm $^{-2}$ with small EOT of $\sim 1$ nm, which is similar to the highest mobility reported so far at such small EOT range.

AlN has successfully been applied to passivate the oxide/III–V interface; however, it changes both the metal work function (WF) and band alignment of the gate-stack and, thus, affects the power consumption of the devices. We found that the AlN layer induces a dipole $\delta = 0.18$ eV between HfO2 and substrate. The dipole value obtained from capacitance–voltage characteristics performs good agreement with the results of X-ray photoelectron spectroscopic measurements. The effective WF of Ni is found to be 5.55 eV, which is larger than its WF in vacuum. The valance band offset and the conduction band offset of HfO2 with AlN/In0.53Ga0.47As are found to be 2.82 and 2.06 eV, respectively.

This work reports the effect of x-ray radiation on In2O5Sn based Transparent Gate Recessed Channel (TGRC) MOSFET with the high-k dielectric at the sub-20 nm regime. Reliability of TGRC-MOSFET with a high-k dielectric in harsh radiation environment (x-ray radiation in the 1k to 10k rad dose range after irradiation) is the main aim of this analysis using TCAD simulation. Results reveal that HfO2 as a gate stack on SiO2 improves the device reliability and enhances the drain current, hole trap density, threshold voltage shift, and radiation sensitivity as compared to Al2O3 and ZrO2 gate stack with 1k rad to 10 k rad radiation doses. Trap/de-trap model has been used for interface charging as well as insulator along with the electron-hole pair generation and recombination. Further, the thermal effect on threshold voltage and sensitivity has also been evaluated. Results suggest that the proposed device with a high-k dielectric is more reliable in the x-ray radiation environment at the sub 20 nm scale. This device finds enormous applications in the clinical and space environment along with signal amplification and a processing circuit.