1. A Reconfigurable and Scalable FPGA Architecture for Bilateral Filtering
- Author
-
Swapnil D. Dabhade, G. N. Rathna, and Kunal N. Chaudhury
- Subjects
Computer science ,020208 electrical & electronic engineering ,ComputingMethodologies_IMAGEPROCESSINGANDCOMPUTERVISION ,Image processing ,02 engineering and technology ,Parallel computing ,Reconfigurable computing ,Computer Science::Hardware Architecture ,Kernel (image processing) ,Control and Systems Engineering ,Gate array ,Computer Science::Computer Vision and Pattern Recognition ,Scalability ,0202 electrical engineering, electronic engineering, information engineering ,020201 artificial intelligence & image processing ,Algorithm design ,Bilateral filter ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,Electrical and Electronic Engineering ,Field-programmable gate array ,Electrical Engineering - Abstract
Bilateral filter is an edge-preserving smoother that has applications in image processing, computer vision, and computational photography. In the past, field-programmable gate array (FPGA) implementations of the filter have been proposed that can achieve high throughput using parallelization and pipelining. An inherent limitation with direct implementations is that their complexity scales as $O(\omega ^2)$ with the filter width $\omega$ . In this paper, we propose an FPGA implementation of a fast bilateral filter that requires just $O(1)$ operations for any arbitrary $\omega$ . The attractive feature of the FPGA implementation is that it is both scalable and reconfigurable. To the best of our knowledge, this is the first scalable FPGA implementation of the bilateral filter. As an application, we use the FPGA implementation for image denoising.
- Published
- 2018