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International audience; Increased capabilities such as recognition and self-adaptability are now required from IoT applications. While IoT node power consumption is a major concern for these applications, cloud-based processing is becoming unsustainable due to continuous sensor or image data transmission over the wireless network. Thus optimized ML capabilities and data transfers should be integrated in the IoT node. Moreover, IoT applications are torn between sporadic data-logging and energy-hungry data processing (e.g. image classification). Thus, the versatility of the node is key in addressing this wide diversity of energy and processing needs. This paper presents SamurAI, a versatile IoT node bridging this gap in processing and in energy by leveraging two on-chip sub-systems: a low power, clock-less, event-driven Always-Responsive (AR) part and an energy-efficient On-Demand (OD) part. AR contains a 1.7MOPS event-driven, asynchronous Wake-up Controller (WuC) with a 207ns wake-up time optimized for sporadic computing, while OD combines a deep-sleep RISC-V CPU and 1.3TOPS/W Machine Learning (ML) for more complex tasks up to 36GOPS. This architecture partitioning achieves best in class versatility metrics such as peak performance to idle power ratio. On an applicative classification scenario, it demonstrates system power gains, up to 3.5x compared to cloud-based processing, and thus extended battery lifetime.

In the context of high-performance computing, the integration of more computing capabilities with generic cores or dedicated accelerators for artificial intelligence (AI) application is raising more and more challenges. Due to the increasing costs of advanced nodes and the difficulties of shrinking analog and circuit input output signals (IOs), alternative architecture solutions to single die are becoming mainstream. Chiplet-based systems using 3D technologies enable modular and scalable architecture and technology partitioning. Nevertheless, there are still limitations due to chiplet integration on passive interposers—silicon or organic. In this article we present the first CMOS active interposer, integrating: 1) power management without any external components; 2) distributed interconnects enabling any chiplet-to-chiplet communication; and3) system infrastructure, design-for-test, and circuit IOs. The IntAct circuit prototype integrates six chiplets in FDSOI 28-nm technology, which are 3D-stacked onto this active interposer in 65-nm process, offering a total of 96 computing cores. Full scalability of the computing system is achieved using an innovative scalable cache-coherent memory hierarchy, enabled by distributed network-on-chips, with 3-Tbit/s/mm2 high bandwidth 3D-plug interfaces using 20- $\mu \text{m}$ pitch micro-bumps, 0.6-ns/mm low latency asynchronous interconnects, while the six chiplets are locally power-supplied with 156-mW/mm2 at 82%-peak-efficiency dc–dc converters through the active interposer. Thermal dissipation is studied showing the feasibility of such approach.

International audience; IoT node application requirements are torn between sporadic data-logging and energy-hungry data processing (e.g. image classification). This paper presents a versatile IoT node covering this gap in processing and energy by leveraging two on-chip sub-systems: a low power, clock-less, event-driven Always-Responsive (AR) part and an energy-efficient On-Demand (OD) part. The AR contains a 1.7MOPS event-driven, asynchronous Wake-up Controller (WuC) with 207ns wake-up time optimized for short sporadic computing. OD combines a deep-sleep RISC-V CPU and 1.3TOPS/W Machine Learning (ML) and crypto accelerators for more complex tasks. The node can perform up to 36GOPS while achieving 15,000x reduction from peak-to-idle power consumption. The interest of this versatile architecture is demonstrated with 105μW daily average power on an applicative classification scenario

This article presents an ultra-low-power parallel computing platform and its system-on-chip (SoC) embodiment, targeting a wide range of emerging near-sensor processing tasks for Internet of Things (IoT) applications. The proposed SoC achieves 193 million operations per second (MOPS) per mW at 162 MOPS (32 bits), improving the first-generation Parallel Ultra-Low-Power (PULP) architecture by 6.4 and 3.2 times in performance and energy efficiency, respectively.

International audience; Emerging nonvolatile memories (NVM) based on resistive switching mechanism such as RRAM are under intense R&D investigation by both academics and industries. They provide high write/read speed, low power, and good endurance (e.g., >10$^{12}$) beyond mainstream NVMs, enabling them to be a good candidate for Flash replacement in microcontroller unit. This replacement could significantly decrease the power consumption and the integration cost on advanced CMOS nodes. This paper presents first the HfO$_2$-based RRAM technology and the associated compact model, which includes related physics and model card fitting experimental electrical characterizations. The 128 kb memory architecture based on RRAM technology and 28 nm fully depleted silicon on insulator (FDSOI) CMOS core process is presented with a bottom-up approach, starting from the bit-cell definition up to the complete memory architecture implementation. The key points of the architecture are the use of standard logic MOS exclusively, avoiding any high voltage MOS usage, program/verify procedure to mitigate cycle to cycle variability issue and direct bit-cell read access for characterization purpose. The proposed architecture is validated using postlayout simulations on MOS and RRAM corner cases.

In this paper, we examine the problem of the drift of the low-resistance state (LRS) in phase change memories based on C or N doped and undoped Ge-rich Ge2Sb2Te5. A novel procedure, named R-SET technique, is proposed to boost the SET speed of these innovative phase change materials by overcoming the decrease of crystallization speed caused by Ge enrichment. The R-SET technique allows, at the same time, an optimized SET programming of the memory cell and the reduction of the LRS drift with respect to standard SET procedures. A circuit that generates the desired R-SET pulse based on a time reference scheme is proposed and discussed.

International audience; Emerging non-volatile memories based on resistive switching mechanisms attract intense R&D efforts from both academia and industry. Oxide-based Resistive Random Acces Memories (OxRAM) gather noteworthy performances, such as fast write/read speed, low power and high endurance outperforming therefore conventional Flash memories. To fully explore new design concepts such as distributed memory in logic, OxRAM compact models have to be developed and implemented into electrical simulators to assess performances at a circuit level. In this paper, we present compact models of the bipolar OxRAM memory based on physical phenomenons. This model was implemented in electrical simulators for single device up to circuit level. J. Low Power Electron. Appl. 2014, 4 2

Emerging nonvolatile memories (eNVMs) such as phase-change random access memories (PCRAMs) or oxide-based resistive random access memories (OxRRAMs) are promising candidates to replace Flash and Static Random Access Memories in many applications. This paper introduces a novel set of building blocks for field-programmable gate arrays (FPGAs) using eNVMs. We propose an eNVM-based configuration point, a look-up table structure with reduced programming complexity and a high-performance switchbox arrangement. We show that these blocks yield an improvement in area and write time of up to 3× and 33×, respectively, versus a regular Flash implementation. By integrating the designed blocks in an FPGA, we demonstrate an area and delay reduction of up to 28% and 34%, respectively, on a set of benchmark circuits. These reductions are due to the eNVM 3-D integration and to their low on-resistance state value. Finally, we survey many flavors of the technologies and we show that the best results in terms of area and delay are obtained with Pt/TiO2/Pt stack, while the lowest leakage power is achieved by InGeTe stack.

International audience; In this paper, we investigate in depth Forming, SET, and Retention of conductive-bridge random-access memory (CBRAM). A kinetic Monte Carlo model of the CBRAM has been developed considering ionic hopping and chemical reaction dynamics. Based on inputs from ab initio calculations and the physical properties of the materials, the model offers the simulation of both the Forming/SET and the Data Retention operations. It aims to create a bond between the physics at atomic level and the device behavior. From the model and experimental results obtained on decananometric devices, we propose an understanding of the physical mechanisms involved in the CBRAM operations. Using the consistent Forming/SET and Data Retention model, we obtained good agreement with the experimental data. Finally, the impact of each layer of the CBRAM on the Forming/SET behavior is decorrelated, allowing an optimization of the performance.

International audience; 3D integration technology is nowadays mature enough, offering today further system integration using heterogeneous technologies, with already many different industrial successes (Imagers, 2.5D Interposers, 3D Memory Cube, etc.). CEA-LETI has been developing for a decade 3D integration, and have pursued research in both directions: developing advanced 3D technology bricks (TSVs, µ-bumps, Hybrid Bonding, etc), and designing advanced 3D circuits as pioneer prototypes. In this paper, a short overview of some recent advanced 3D technology results is presented, including some latest 3D circuit's description.

International audience; “Normally Off, Instantly On” applications are becoming common in our environment. They range from healthcare to video surveillance. As the number of applications and their associated performance requirements grow rapidly, more and more powerful, flexible, and power efficient computing units are necessary. In such a context, Field Programmable Gate Arrays (FPGA) architectures present a good trade-off between performance and flexibility. However, they consume high static power and can hardly be associated with power-gating techniques due to their long context-restoring phase. In this paper, we propose to integrate non-volatile resistive memories in the configuration cells and registers in order to instantly restore the FPGA context. If the circuit is in the ‘ON’ state for less than 42% of time, non-volatile FPGA starts saving energy compared to classical FPGA. Finally, when context-saving functionality is included, for a typical application with only 1% of time spent in the ‘ON’ state, the energy gain exceeds 40%

For the rapid adoption of new and aggressive technologies such as ambipolar Silicon NanoWire (SiNW), addressing fault-tolerance is necessary. Traditionally, transient fault detection implies large hardware overhead or performance decrease compared to permanent fault detection. In this paper, we focus on on-line testing and its application to ambipolar SiNW. We demonstrate on self - checking ripple - carry adder how ambipolar design style can help reduce the hardware overhead. When compared with equivalent CMOS process, ambipolar SiNW design shows a reduction in area of at least 56% (28%) with a decreased delay of 62% (6%) for Static (Transmission Gate) design style.

International audience; In this paper, we model system-on-chip (SoC) con- sumption as a dynamic process that can be easily tracked over time through a set of power modes. The proposed method provides precise information on each block dissipation inside the system. Each generated mode defines a specific model that links power to block activity reported by a set of critical signals. The modeling approach is illustrated by real experiments. When ap- plied to memory blocks, the model showed 10% maximum error, considering power at very fine granularity (quasi-instantaneous power). For long simulations, average and maximum energy are estimated with an error of 5.3% and 4.8%, respectively. For a memory controller and a MAC unit, only one probe is used leading to a very limited area overhead.

International audience; This work presents a Non-Volatile SRAM (NV-SRAM) cell, resilient to information loss. The cell features fast storage (20ns) for the operating voltage of 1.0V. The information is backed-up during POWER-DOWN/ RECOVERY cycle in two bipolar Oxide Resistive RAMs (OxRRAMs). The proposed NV-SRAM is designed with an 8T2R structure using 22nm FDSOI technology and resistive memory devices based on HfO 2. The stability and the reliability of the NV-SRAM cell is investigated by taking into account the variability of the transistors. It is shown that high R OFF /R ON is necessary to ensure reliable RECOVERY operation and high SRAM yield under cell area and power consumption constraints.

International audience; —Resistive Random Access Memories (ReRAMs) fabricated in the back-end-of-line are a promising breakthrough for including permanent retention mechanisms in embedded systems. This low-cost solution opens the way to advanced power management schemes. In this paper, we propose novel design architecture of a non-volatile flip-flop based on Bipolar ReRAMs (Bi-RNVFF). Compared to state-of-the-art Data-Retention flip-flop (with Balloon latch), the proposed design is 25% smaller due to 6T structure compared to the 8T structure of Data-Retention flip-flop. Moreover, being non-volatile, the proposed architecture exhibits a zero leakage compared to a Data-Retention Flip-Flop, which consumes ~3.2µW in sleep mode (leakage) for a 10K Flip-Flop design implemented in 22nm FDSOI technology. Our simulation results show that Bi-RNVFF is a true alternative for future " Power-on, Power-off " application adding Non-Volatility without significant burdening of the existing architectures.

While traditional cluster computers are more constrained by power and cooling costs for solving extreme-scale (or exascale) problems, the continuing progress and integration levels in silicon technologies make possible complete end-user systems on a single chip. This massive level of integration makes modern multicore chips all pervasive in domains ranging from climate forecasting and astronomical data analysis, to consumer electronics, smart phones, and biological applications. Consequently, designing multicore chips for exascale computing while using the embedded systems design principles looks like a promising alternative to traditional cluster-based solutions. This paper aims to present an overview of new, far-reaching design methodologies and run-time optimization techniques that can help breaking the energy efficiency wall in massively integrated single-chip computing platforms.

International audience; With forecasted hundreds of processing elements (PEs), future embedded systems will be able to handle multiple applications with very diverse running constraints. Systems will integrate distributed decision capabilities. In order to control the power and temperature, dynamic voltage frequency scalings (DVFSs) are applied at PE level. At system level, it implies to dynamically manage the different voltage/frequency couples of each tile to obtain a global optimization. This paper introduces a scalable multiobjective approach based on game theory, which adjusts at run-time the frequency of each PE. It aims at reducing the tile temperature while maintaining the synchronization between application tasks. Results show that the proposed run-time algorithm requires an average of 20 calculation cycles to find the solution for a 100-processor platform and reaches equivalent performances when comparing with an offline method. Temperature reductions of about 23% were achieved on a demonstrative test-case.

Monolithic 3D Integration (3DMI) consists in processing transistors on top of each other sequentially. This technology appears to be an alternative solution to scaling, from the 7nm node integration and below, as substantial gain in area and performance as compared to planar technology is expected without scaling the transistor technology node. 3DMI appears to be the most optimized way to take advantage of the vertical dimension as almost no alignment constraints remains. By using a standard lithography, the top transistors can be aligned directly onto their bottom counterparts with a high accuracy (see Fig. 1), contrary to TSV-based 3D technologies [2]. Furthermore, 3DMI is a highly versatile technology as the different transistor levels can be optimized independently, from the choice of the channel characteristics (e.g. material, orientation, strain) to the architecture itself (e.g. CMOS on CMOS, PMOS on NMOS, FinFET on BULK, LVT on RVT) [3]. Such sequential integration raises two main technological challenges: - Creating an active layer above a bottom transistor which will become the channel of the top transistor. In order to achieve similar performance for top FET than bottom FET, the substrate quality must be equivalent than commercial substrates. Thus, this layer must be monocristalline and defect free in order to optimize the mobility and to be consistent with high performance criteria. A precise thickness control is also necessary in order to avoid device performance dispersion. - Realizing a high performance top transistor level without degrading the bottom level as the stacked transistor levels are processed sequentially, i.e. at low temperature process –typically below 600°C. Recent results demonstrate some integration solutions, such as junction activation by Solid Phase Epitaxy Regrowth below 600°C [4]. To tackle the first challenge, we transfer a thin silicon layer from a high quality Silicon On Insulator (SOI) wafer by direct bonding. It appears to be the most effective solution to obtain a defect free monocristalline active layer with a well-controlled thickness. This method is preferred to different techniques which have been developed to create large monocristal grains of silicon either by laser anneal of amorphous Poly-Silicon [5] or by µ-Czochralsky process [6]. However, in both cases, large “seed layers” are necessary to control the orientation and the size of these grains, which is not consistent with for high density circuits. For this layer transfer, a blanket SOI wafer on which a Si02 layer is either grown or deposited, is bonded on the classical pre-metal dielectric above the bottom transistor level. The SOI backside is then removed by grinding and chemical etching to keep only the silicon layer. While expert knowledge has been reached for full sheet wafer bonding, the situation on a patterned layer can be really challenging with the design rules of 3DMI. In order to face these challenges, the surface preparation, the direct bonding process and the thinning steps have been optimized to prevent any defect on the whole 300mm surface. Also TMAH bevel edge protection and silicide protection layer have been added. This work will give a general overview of 3D monolithic challenges. Also, a specific focus will be made on direct bonding which is a major enabler of this type of integration. Indeed among the other alternative techniques, it appears to be the best solution to meet the high performance and high density criteria. REFERENCES: [1] P. Batude et al., VLSI Technology, pp. 158 (2011) [1] P. Batude et al., ECS Spring meeting, (16) pp. 47 (2008) [2] P. Batude et al., IITC-AMC (2014) [3] P. Batude et al., IEDM, pp.731-734 (2011) [4] C-H. Shen et al., IEDM, pp. 931-934 (2013) [5] J. Derakhshandeh et al., TED vol.58, no. 11 (2011) Fig.1: 3DMI demonstration with ultra-high alignment between the stacked transistors [1] obtained with 248nm stepper.

International audience; Double-gate carbon nanotube field effect transistors (DG-CNTFETs) are novel devices showing an interesting property allowing to control the p- or n-type behavior during the device operation. This opens up the opportunity for novel design paradigms. Based on a compact physical model of these devices, we demonstrate the benefit of designing field-programmable gate arrays (FPGAs) using fine-grain DG-CNTFET logic blocs rather than traditional look-up tables and coarse-grain DG-CNTFET logic blocs. In particular, we show a reduction by 13% to 48% on average in terms of delay of FPGA benchmarks. ©The Electrochemical Society.

Several nanowire technologies have emerged recently, providing a way to continue the scaling down of complementary metal-oxide-semiconductor (CMOS) technology. The opportunities offered at the level of logic circuit design depend on the technology properties, and some applications seem to be suitable for specific technologies. In this paper, we survey three nanowire technologies that yield nanowire arrays. All of them depend on the photolithography limit but they differ with respect to the processing and the device properties. We show the ability of the spacer technique to yield nanowires with a pitch below the photolithography limit. We introduce the nanowire crossbars in a pure CMOS process and extract the parasitics that affect nanowire crossbar circuits. Vertically stacked nanowires are also demonstrated with the deep reactive ion etching (DRIE) process. We link the surveyed processes to specific circuit architectures that are optimized for the considered technologies. A nanowire decoder for sub-lithographic nanowires is demonstrated with the smallest size compared to other competing technologies. Then an optimized crossbar multiplexer is presented, which takes into account the presence of parasitics. Finally, a general library of logic gates based on vertically stacked nanowires is evaluated showing a smaller area and a better performance than CMOS.

The thesis is opening towards new technical solutions. The aim of this study is twofold, the first is tominiaturize the electronics to achieve a factor of 10 in integration compared to a conventional CMStechnology, the second is to improve the system in package reliability for aeronautics, defense and space.The first step concerns the manufacture of an assembly composed by a silicon chip and an organicsubstrate. These two entities will allow the study of the report by flip chip. To do so, micro-pillar type copperand tin-silver solder connections, otherwise known as copper pillar, will be used. The impact of differentdesign and assembly parameters on thermal cycles reliability will be studied.In a second step, finite element simulations are carried out on the assemblies in order to obtainpredictions on the reliability during thermal cycles using as a criterion the viscoplastic energy. Thesimulations and the experimental results will eventually be compared, and the gaps will be discussed.Failures analysis during thermal cycles will be based on the analysis of copper pillar interconnectionsby micro-sections and SEM and EBSD imaging. Thickness changing in intermetallic, cracking in the solder aswell as grain size and recrystallization phenomena will be presented and commented.The final objectives of this work are, from an academic point of view, to highlight first of all, theC2 - Restrictedbehaviors involved in the reliability of such interconnections in a binding thermo-mechanical environment,and moreover, the failure mechanisms. Then, it is to establish a predict life model that is representative ofthe experimental results obtained. Finally, it will define design rules that can then be used at Safran for therealization of SIP., La thèse s’inscrit dans un contexte d’ouverture vers de nouvelles solutions techniques. L’objectif quiest porté par cette étude est double, le premier est de miniaturiser l’électronique pour atteindre un gaind’un facteur 10 en intégration par rapport à une technologie CMS classique, le second est d’améliorer lafiabilité des assemblages de type « System In Package » ainsi obtenus pour les domaines aéronautique,défense et spatial.La première phase de travail concerne la fabrication d’un assemblage composé d’une puce en siliciumet d’un substrat organique. Ces deux entités permettront l’étude du report par flip chip. Pour ce faire, desconnexions de type micro-piliers en cuivre et en alliage étain-argent, autrement appelées « copper pillar »seront mises en place. L’impact des différents paramètres de conception et d’assemblage sur la fiabilité encycles thermiques seront étudiés.Dans une seconde phase, des simulations par éléments finis sont effectuées sur les assemblages afind’obtenir des prédictions sur la fiabilité au cours de cycles thermiques en utilisant comme critère l’énergieviscoplastique. Les simulations et les résultats expérimentaux seront finalement comparés et les écartsseront discutés.L’analyse de défaillances au cours des cycles thermiques reposera sur l’analyse des interconnexions« copper pillar » par micro-sections et imagerie SEM et EBSD. Les évolutions d’épaisseur d’intermétalliques,des fissurations dans la brasure ainsi que la taille des grains et les phénomènes de recristallisation serontprésentés et commentés.Les objectifs finaux de ce travail sont, d‘un point de vue académique, de mettre en lumière toutd’abord, les comportements mis en jeu dans la fiabilité de telles interconnexions dans un environnementthermo-mécanique contraignant, et, par ailleurs, les mécanismes de défaillance. Ensuite, il s’agit d’établirun modèle de vieillissement qui soit représentatif des résultats expérimentaux obtenus. Enfin, il s’agira dedéfinir des règles de conception qui pourront ensuite être utilisées au niveau de Safran pour la réalisationdes assemblages SIP intégrés dans des systèmes embarqués.

The application constraints driving the design of embedded systems are constantly demanding higher performance and power efficiency. To meet these constraints, current SoC platforms rely on replicating several processing cores while adding dedicated hardware accelerators to handle specific tasks. However, developing embedded applications is becoming a key challenge, since applications workload will continue to grow and the software technologies are not evolving as fast as hardware architectures, leaving a gap in the full system design. Indeed, the increased programming complexity can be associated to the lack of software standards that supports heterogeneity, frequently leading to custom solutions. On the other hand, implementing a standard software solution for embedded systems might induce significant performance and memory usage overheads. Therefore, this Thesis focus on decreasing this gap by implementing hardware mechanisms in co-design with a standard programming interface for embedded systems. The main objectives are to increase programmability through the implementation of a standardized communication application programming interface (MCAPI), and decrease the overheads imposed by the software implementation through the use of the developed hardware mechanisms.The contributions of the Thesis comprise the implementation of MCAPI for a generic multi-core platform and dedicated hardware mechanisms to improve communication connection phase and overall performance of data transfer phase. It is demonstrated that the proposed mechanisms can be exploited by the software implementation without increasing software complexity. Furthermore, performance estimations obtained using a SystemC/TLM simulation model for the reference multi-core architecture show that the proposed mechanisms provide significant gains in terms of latency (up to 97%), throughput (40x increase) and network traffic (up to 68%) while reducing processor workload for both characterization test-cases and real application benchmarks., L’évolution des contraintes applicatives imposent des améliorations continues sur les performances et l’efficacité énergétique des systèmes embarqués. Pour répondre à ces contraintes, les plateformes « SoC » actuelles s’appuient sur la multiplication des cœurs de calcul, tout en ajoutant des accélérateurs matériels dédiés pour gérer des tâches spécifiques. Dans ce contexte, développer des applications embarquées devient un défi complexe, en effet la charge de travail des applications continue à croître alors que les technologies logicielles n’évoluent pas aussi vite que les architectures matérielles, laissant un écart dans la conception complète du système. De fait, la complexité accrue de programmation peut être associée à l’absence de standards logiciels qui prennent en charge l’hétérogénéité des architectures, menant souvent à des solutions ad hoc. A l’opposé, l’utilisation d’une solution logicielle standardisée pour les systèmes embarqués peut induire des surcoûts importants concernant les performances et l’occupation de la mémoire si elle n’est pas adaptée à l’architecture. Par conséquent, le travail de cette thèse se concentre sur la réduction de cet écart en mettant en œuvre des mécanismes matériels dont la conception prend en compte une interface de programmation standard pour systèmes embarqués. Les principaux objectifs sont ainsi d’accroître la programmabilité par la mise en œuvre d’une interface de programmation : MCAPI, et de diminuer la charge logiciel des cœurs grâce à l’utilisation des mécanismes matériels développés.Les contributions de la thèse comprennent la mise en œuvre de MCAPI pour une plate-forme multicœur générique et des mécanismes matériels pour améliorer la performance globale de la configuration de la communication et des transferts de données. Il est démontré que les mécanismes peuvent être pris en charge par les interfaces logicielles sans augmenter leur complexité. En outre, les résultats de performance obtenus en utilisant un modèle SystemC/TLM de l’architecture multicœurs de référence montrent que les mécanismes proposés apportent des gains significatifs en termes de latence, débit, trafic réseau, temps de charge processeur et temps de communication sur des cas d’étude et des applications complètes.

Scaling limitations of advanced technology nodes are increasing and the BEOL parasitics are becoming more dominant. This has led to an increasing interest in 3D technologies to overcome such limitations and to continue the scaling predicted by Moore's Law. 3D technologies vary according to the fabrication process which creates a wide spectrum of technologies including Through-Silicon-VIA (TSV), Copper-to-Copper (CuCu) and Monolithic 3D (M3D). TSV and CuCu provide 3D contacts of pitch around 5-10um while M3D scales down 3D via pitch extremely to 0.11um. Such high-density capability of Monolithic 3D technology creates new design paradigms. In this context, our objective is to propose innovative design methodologies to well utilize M3D technology and introduce a technology assessment framework to evaluate different M3D technology parameters from design perspective.This thesis can be divided into three main contributions. As creating 3D standard cells become achievable thanks to M3D technology, a new 3D standard cell approach has been introduced which we call it ‘3D Cell-on-Buffer' (3DCoB). 3DCoB cells are created by splitting 2D cells into functioning gates and driving buffers stacked over each other. The simulation results show gain in timing performances compared to 2D. By applying an additionally Multi-VDD low-power approach, iso-performance power gain has been achieved. Afterwards cell-on-cell design approach has been explored where a partitioning methodology is needed to distribute cells between different tiers, i.e. determine which cell is placed on which tier. A physical-aware partitioning methodology has been introduced which improves power-performance-area results comparing to the state-of-the-art partitioning techniques. Finally a full high-density 3D technology assessment study is presented to explore the trade-offs between different 3D technologies, block complexities and partitioning methodologies., L'impact des interconnections d'un circuit intégré sur les performances et la consommation est de plus en plus important à partir du nœud CMOS 28 nm et au-delà, ayant pour effet de minimiser de plus ne plus la loi de Moore. Cela a motivé l'intérêt des technologies d'empilement 3D pour réduire l'effet des interconnections sur les performances des circuits. Les technologies d'empilement 3D varient suivant différents procédés de fabrication d'où l'on mettra en avant la technologie Trough Silicon Via (TSV) – Collage Cuivre-Cuivre (Cu-Cu) et 3D Monolithique. TSV et Cu-Cu présentent des diamètres d'interconnexions 3D de l'ordre de 10 µm tandis que le diamètre d'une interconnexion 3D Monolithique est 0.1 µm, c'est-à-dire cent fois plus petit. Un tel diamètre d'interconnexion créée de nouveaux challenge en terme de conception de circuit intégré numérique. Dans ce contexte, notre objectif est de proposer des méthodologies de conception de circuits 3D innovantes afin d'utiliser au mieux la densité d'intégration possible et d'évaluer efficacement les gains en performance, surface et consommation potentiels de ces différentes technologies d'empilement par rapport à la conception de circuit 2D.Trois contributions principales constituent cette thèse : La densité d'intégration offerte par les technologies d'empilement étudiées laisse le possibilité de revoir la topologie des cellules de bases en les concevant directement en 3D. C'est ce qui a été fait dans l'approche Cellule sur Buffer (Cell-on-Buffer – CoB), en empilant la fonction logique de base d'une cellule sur l'étage d'amplification. Les simulations montrent des gains substantiels par rapport aux circuits 2D. On a imaginé par la suite désaligner les niveaux d'alimentation de chaque tranche afin de créer une technique de Multi-VDD adaptée à l'empilement 3D pour réduire encore plus la consommation des circuits 3D.Dans un deuxième temps, le partitionnement grain fin des cellules a été étudié. En effet au niveau VLSI, quand on conçoit un circuit de plusieurs milliers voir million de cellules standard en 3D, se pose la question de l'attribution de telle ou telle cellule sur la tranche haute ou basse du circuit 3D afin d'accroitre au mieux les performances et consommation du circuit 3D. Une méthodologie de partitionnement physique est introduite pour cela.Enfin un environnement d'évaluation des performances et consommation des technologies 3D est présenté avec pour objectif de rapidement tester les gains possibles de telle ou telle technologie 3D tout en donnant des directives quant à l'impact des certains paramètres technologiques 3D sur les performances et consommation.

Semiconductor memory has always been an indispensable component of modern electronic systems. The increasing demand for highly scaled memory devices has led to the development of reliable non-volatile memories that are used in computing systems for permanent data storage and are capable of achieving high data rates, with the same or lower power dissipation levels as those of current advanced memory solutions.Among the emerging non-volatile memory technologies, Phase Change Memory (PCM) is the most promising candidate to replace conventional Flash memory technology. PCM offers a wide variety of features, such as fast read and write access, excellent scalability potential, baseline CMOS compatibility and exceptional high-temperature data retention and endurance performances, and can therefore pave the way for applications not only in memory devices, but also in energy demanding, high-performance computer systems. However, some reliability issues still need to be addressed in order for PCM to establish itself as a competitive Flash memory replacement.This work focuses on the study of embedded Phase Change Memory in order to optimize device performance and propose solutions to overcome the key bottlenecks of the technology, targeting high-temperature applications. In order to enhance the reliability of the technology, the stoichiometry of the phase change material was appropriately engineered and dopants were added, resulting in an optimized thermal stability of the device. A decrease in the programming speed of the memory technology was also reported, along with a residual resistivity drift of the low resistance state towards higher resistance values over time.A novel programming technique was introduced, thanks to which the programming speed of the devices was improved and, at the same time, the resistance drift phenomenon could be successfully addressed. Moreover, an algorithm for programming PCM devices to multiple bits per cell using a single-pulse procedure was also presented. A pulse generator dedicated to provide the desired voltage pulses at its output was designed and experimentally tested, fitting the programming demands of a wide variety of materials under study and enabling accurate programming targeting the performance optimization of the technology., Les mémoires à base de semi-conducteur sont indispensables pour les dispositifs électroniques actuels. La demande croissante pour des dispositifs mémoires fortement miniaturisées a entraîné le développement de mémoires non volatiles fiables qui sont utilisées dans des systèmes informatiques pour le stockage de données et qui sont capables d'atteindre des débits de données élevés, avec des niveaux de dissipation d'énergie équivalents voire moindres que ceux des technologies mémoires actuelles.Parmi les technologies de mémoires non-volatiles émergentes, les mémoires à changement de phase (PCM) sont le candidat le plus prometteur pour remplacer la technologie de mémoire Flash conventionnelle. Les PCM offrent une grande variété de fonctions, comme une lecture et une écriture rapide, un excellent potentiel de miniaturisation, une compatibilité CMOS et des performances élevées de rétention de données à haute température et d'endurance, et peuvent donc ouvrir la voie à des applications non seulement pour les dispositifs mémoires, mais également pour les systèmes informatiques à hautes performances. Cependant, certains problèmes de fiabilité doivent encore être résolus pour que les PCM se positionnent comme un remplacement concurrentiel de la mémoire Flash.Ce travail se concentre sur l'étude de mémoires à changement de phase intégrées afin d'optimiser leurs performances et de proposer des solutions pour surmonter les principaux points critiques de la technologie, ciblant des applications à hautes températures. Afin d'améliorer la fiabilité de la technologie, la stœchiométrie du matériau à changement de phase a été conçue de façon appropriée et des dopants ont été ajoutés, optimisant ainsi la stabilité thermique. Une diminution de la vitesse de programmation est également rapportée, ainsi qu'un drift résiduel de la résistance de l'état de faiblement résistif vers des valeurs de résistance plus élevées au cours du temps.Une nouvelle technique de programmation est introduite, permettant d'améliorer la vitesse de programmation des dispositifs et, dans le même temps, de réduire avec succès le phénomène de drift en résistance. Par ailleurs, un algorithme de programmation des PCM multi-bits est présenté. Un générateur d'impulsions fournissant des impulsions avec la tension souhaitée en sortie a été conçu et testé expérimentalement, répondant aux demandes de programmation d'une grande variété de matériaux innovants et en permettant la programmation précise et l’optimisation des performances des PCM.

The constant evolution of the data storage needs over the last decades have led the technological landscape to completely change and reinvent itself. From the early stage of magnetic storage to the most recent solid state devices, the bit density keeps increasing toward what seems from a consumer point of view infinite storage capacity and performances. However, behind each storage technology transition stand density and performances limitations that required strong research work to overcome. This manuscript revolves around one of the promising emerging technology aiming to revolutionize data storage landscape: the Conductive Bridge Random Access Memory (CBRAM). This technology based on the reversible formation and dissolution of a conductive path in a solid electrolyte matrix offers great advantages in term of power consumption, performances, density and the possibility to be integrated in the back end of line. However, for this technology to be competitive some roadblocks still have to be overcome especially regarding the technology variability, reliability and thermal stability. This manuscript proposes a comprehensive understanding of the CBRAM operations based on experimental results and a specially developed Kinetic Monte Carlo model. This understanding creates bridges between the physical properties of the materials involved in the devices and the devices performances (Forming, SET and RESET time and voltage, retention, endurance, variability). A strong emphasis is placed on the current limitations of the technology previously stated and how to overcome these limitations. Improvement of the thermal stability and device reliability are demonstrated with optimized operating conditions and proper devices engineering., Ces dernières décennies, la constante évolution des besoins de stockage de données a mené à un bouleversement du paysage technologique qui s’est complètement métamorphosé et réinventé. Depuis les débuts du stockage magnétique jusqu’aux plus récents dispositifs fondés sur l’électronique dit d’état solide, la densité de bits stockés continue d’augmenter vers ce qui semble du point de vue du consommateur comme des capacités de stockage et des performances infinies. Cependant, derrière chaque transition et évolution des technologies de stockage se cachent des limitations en termes de densité et performances qui nécessitent de lourds travaux de recherche afin d’être surmontées et repoussées. Ce manuscrit s’articule autour d’une technologie émergeante prometteuse ayant pour vocation de révolutionner le paysage du stockage de données : la mémoire à pont conducteur ou Conductive Bridge Random Access Memory (CBRAM). Cette technologie est fondée sur la formation et dissolution réversible d’un chemin électriquement conducteur dans un électrolyte solide. Elle offre de nombreux avantages face aux technologies actuelles tels qu’une faible consommation électrique, de très bonnes performances d’écriture et de lecture et la capacité d’être intégré aux seins des interconnexions métalliques d’une puce afin d’augmenter la densité de stockage. Malgré tout, pour que cette technologie soit compétitive certaines limitations ont besoin d’être surmontées et particulièrement sa variabilité et sa stabilité thermique qui posent encore problème. Ce manuscrit propose une compréhension physique globale du fonctionnement de la technologie CBRAM fondée sur une étude expérimentale approfondie couplée à un modèle Monte Carlo cinétique spécialement développé. Cette compréhension fait le lien entre les propriétés physiques des matériaux composant la mémoire CBRAM et ses performances (Tension et temps d’écriture et d’effacement, rétention de donnée, endurance et variabilité). Un fort accent est mis la compréhension des limites actuelle de la technologie et comment les repousser. Grâce à une optimisation des conditions d’opérations ainsi qu’à un travail d’ingénierie des dispositifs mémoire, il est démontré dans ce manuscrit une forte amélioration de la stabilité thermique ainsi que de la variabilité des états écrits et effacés.

The ever increasing complexity of digital systems leads the reconfigurable architectures such as Field Programmable Gate Arrays (FPGA) to become highly demanded because of their in-field (re)programmability and low nonrecurring engineering (NRE) costs. Reconfigurability is achieved with high number of point configuration memories which results in extreme application flexibility and, at the same time, significant overheads in area, performance, and power compared to Application Specific Integrated Circuits (ASIC) for the same functionality. In this thesis, we propose to design FPGAs with several 3D technologies for efficient FPGA circuits. First, we integrate resistive memory based blocks to reduce the routing wirelength and widen FPGA employability for low-power applications with non-volatile property. Among many technologies, we focus on Oxide Resistive Memory (OxRRAM) and Conductive Bridge Resistive Memory (CBRAM) devices by assessing unique properties of these technologies in circuit design. As another solution, we design a new FPGA with 3D monolithic integration (3DMI) by utilizing high-density interconnects. Starting from two layers with logic-on-memory approach, we examine various partitioning schemes with increased number of integrated active layers to reduce the routing complexity and increase logic density. Based on the obtained results, we demonstrate that multi-tier 3DMI is a strong alternative for future scaling., La complexité croissante des systèmes numériques amène les architectures reconfigurable telles que les Field Programmable Gate Arrays (FPGA) à être très fortement demandés en raison de leur facilité de (re)programmabilité et de leurs faibles coûts non récurrents (NRE). La re-configurabilité est réalisée grâce à de nombreux point mémoires de configuration. Cette re-configurabilité se traduit par une extrême flexibilité des applications implémentées et dans le même temps par une perte en surface, en performances et en puissance par rapport à des circuits intégrés spécifiques (ASIC) pour la même fonctionnalité. Dans cette thèse, nous proposons la conception de FPGA avec différentes technologies 3D pour une meilleure efficacité. Nous intégrons les blocs à base de mémoire résistives pour réduire la longueur des fils de routage et pour élargir l'employabilité des FPGAs pour des applications non-volatiles de faible consommation. Parmi les nombreuses technologies existantes, nous nous concentrons sur les mémoires à base d'oxyde résistif (OxRRAM) et les mémoires à pont conducteur (CBRAM) en évaluant les propriétés uniques de ces technologies. Comme autre solution, nous avons conçu un nouveau FPGA avec une intégration monolithique 3D (3DMI) en utilisant des interconnexions haute densité. A partir de deux couches avec l'approche logique-sur-mémoire, nous examinons divers schémas de partitionnement avec l'augmentation du nombre de couches actives intégrées pour réduire la complexité de routage et augmenter la densité de la logique. Sur la base des résultats obtenus, nous démontrons que plusieurs niveaux 3DMI est une alternative solide pour l'avenir de mise à l'échelle de la technologie.

For the last four decades, the semiconductor industry has experienced an exponential growth. According to the ITRS, as we advance into the era of nanotechnology, the traditional CMOS electronics is reaching its physical and economical limits. The main objective of this thesis is to explore novel design opportunities for reconfigurable architectures given by the emerging technologies. On the one hand, the thesis will focus on the traditional FPGA architecture scheme, and survey some structural improvements brought by disruptive technologies. While the memories and routing structures occupy the major part of the FPGAs total area and mainly limit the performances, 3-D integration appears as a good candidate to embed all this circuitry into the metal layers. Configuration and routing circuits based on back-end compatible resistive memories, a monolithic 3-D process flow and a prospective vertical FETs process flow are introduced and assessed within a complete architectural context. On the other hand, the thesis will present some novel architectural schemes for ultra-fine grain computing. The size of the logic elements can be reduced thanks to inherent properties of the technologies, such as the crossbar organization or the controllable polarity of carbon electronics. Considering the granularity of the logic elements, specific fixed and incomplete interconnection topologies are required to prevent the large overhead of a configurable interconnection pattern. To evaluate the potentiality of this new architectural scheme, a specific benchmarking flow will be presented in order to explore the ultra-fine grain architectural design space., Durant les quatre dernières décennies, l’industrie des semi-conducteurs a connu une croissance exponentielle. En accord avec l’ITRS et à mesure de l'approche vers le nanomètre, les promesses sont énormes et les composants sont réduits à leurs limites physiques et économiques ultimes. L’objectif principal de cette thèse est d’explorer les opportunités offertes par les technologies émergentes pour la conception d’architectures reconfigurables. Tout d’abord, la thèse se centre sur l’architecture FPGA traditionnelle et étudie des améliorations structurelles apportées par des technologies en ruptures. Tandis que les structures de configuration et de routage occupent la majeure partie de la surface d’un FPGA et limitent ces performances, l’intégration 3-D apparait comme une bonne opportunité pour déplacer ces circuits dans les niveaux métalliques. Des circuits de configuration et de routage utilisant des mémoires résistives compatibles back-end, un procédé d’intégration 3-D ou encore un procédé de réalisation de transistors verticaux seront introduits et évalués dans un contexte architectural complet. Par la suite, la thèse présente de nouvelles propositions architecturales pour la logique à grain ultra-fin. La taille des éléments logiques peut être réduite grâce aux propriétés inhérentes de certaines technologies, telles que l’arrangement en structures entrecroisées de nanofils ou la polarité contrôlable des transistors carbones. Considérant le changement de granularité des opérateurs logiques, des topologies d’interconnexions fixes sont nécessaires afin d’éviter l’important surcoût dû à l’interconnexion programmable. Afin d’étudier les possibilités de cette organisation, un flot d’évaluation est présenté et utilisé pour explorer l’espace de conception relatif aux architectures à grain ultra-fin.