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This paper presents an inductor-less low-power low-voltage cross-coupled regulated cascode (LV CC-RGC) transimpedance amplifier (TIA) design topology with a negative resistance in addition to the traditional gm-boosting approach. Combining the above techniques leads to enhanced design flexibility without needing an on-chip inductor and extra power consumption. It is particularly beneficial as well when the capacitance of a large photodiode (PD) is located at the TIA input. The TIA is implemented in $0.35~\mu $ m CMOS technology with a maximum ft of 20 GHz. Experimental results demonstrate a transimpedance gain of 60 dB $\Omega $ , a 3-dB bandwidth of 1.8 GHz, and an average input-referred noise current spectral density of 9.2 pA/ $\surd $ Hz. The circuit’s power consumption and chip area are 2.2 mW and 0.004 mm2, respectively.

It is shown that the integration of a single-photon avalanche diode (SPAD) together with a BiCMOS gating circuit on one chip reduces the parasitic capacitance a lot and therefore reduces the avalanche build-up time. The capacitance of two bondpads, which are necessary for the connection of an SPAD chip and a gating chip, are eliminated by the integration. The gating voltage transients of the SPAD are measured using an integrated mini-pad and a picoprobe. Furthermore, the gating voltage transients of a CMOS gating circuit and of the BiCMOS gating circuit are compared for the same integrated SPAD. The extension of the 0.35 μm CMOS process by an NPN transistor process module enabled the BiCMOS gating circuit. The avalanche build-up time of the SPAD is reduced to 1.6 ns due to the integration compared to about 3 ns for a wire-bonded off-chip SPAD using the same n+ and p-well as well as the same 0.35 μm technology.

Spot PIN photodiodes were integrated without any process modifications in a high-voltage 0.18 μm CMOS technology. These photodiodes are a combination of vertical and lateral PIN photodiodes using the P+ bulk wafer and a P-type ring at the surface as anodes. Devices with N+ cathode and N+/N-well cathode are compared. A small N+/N-well cathode spot reduces the capacitance to 1.47 fF and the N+ cathode spot leads to a capacitance of 1.07 fF. The light sensitive area of these photodiodes is 707 μm2. Simulated electric field distributions show the full depletion of the spot PIN photodiodes. Responsivities from 0.12 A/W to 0.16 A/W and from 0.50 A/W to 0.52 A/W for 405 nm and 675 nm, respectively, are achieved. The measured bandwidths for 675 nm light are from 520 MHz to 690 MHz at reverse biases from 15 V to 30 V.

A monolithically integrated receiver consisting of a low-capacitance PIN photodiode and a photo-charge integrating amplifier in 0.18-μm CMOS is introduced launching a new class of ultra-sensitive optical receivers. The integrated PIN photodiode has a junction capacitance of 1.5 fF at a light-sensitive diameter of 30 μm, a responsivity of 0.39 A/W at 635 nm, and rise/fall times of 0.73/0.92 ns at a reverse bias of 20 V. The common-source amplifier integrates the photo-charges on the smallest possible integration capacitor, which is a gate-drain overlap capacitance. The data bits are reconstructed by double sampling. In such a way, the sensitivity of SPAD receivers is achieved, however without using any impact ionization. At 50 Mb/s, a sensitivity of −56.4 dBm for a bit error ratio (BER) of 2 × 10−3 is obtained using a wavelength of 635 nm.

This paper presents a CMOS-integrated linear-mode avalanche photodiode based on electric field-line crowding (EFLC-APD) to form an effective multiplication zone and a wide absorption zone. The EFLC-APD possesses a hemispherical avalanching electric field at the n-well/p- epi junction formed due to the curvature of the half-sphere cathode. A lower electric field extends radially across the entire volume of the EFLC-APD towards the substrate and towards the surface anode. Because of such a distribution of the electric field, electrons photogenerated within the whole volume drift towards the cathode. Therefore, the EFLC-APD provides a large sensitive-area to total-area ratio while offering high responsivity and bandwidth for red and near-infrared light due to its thick absorption zone and drift-based carrier transport. It is shown that the electric field distribution can be modified by the design parameters such as cathode radius and diode size in addition to doping profiles. The EFLC-APD achieves a responsivity-bandwidth (R-BW) product of 49.5 $\frac{\mathrm{A}}{\mathrm{W}}\cdot$GHz, corresponding to the responsivity and bandwidth of 33 A/W and 1.5 GHz, respectively, at the wavelength of 850 nm. In addition, a maximum responsivity of 3.05 $\times\, 10^{\mathrm{3}}$ A/W at 2 nW optical power is achieved for the red and near-infrared spectral range. Noise characterization resulted in an excess noise factor F = 6 measured at an avalanche gain of 56.7. Due to the high sensitive-area to total-area ratio, high responsivity, large bandwidth, and CMOS compatibility, this APD is a promising optical detector for many applications.

A gating circuit for a photonic quantum simulator is introduced. The gating circuit uses a large excess bias voltage of up to 9.9 V and an integrated single-photon avalanche diode (SPAD). Nine channels are monolithically implemented in an application-specific integrated circuit (ASIC) including nine SPADs using 0.18 µm high-voltage CMOS technology. The gating circuit achieves rise and fall times of 480 ps and 280 ps, respectively, and a minimum full-width-at-half-maximum pulse width of 1.26 ns. Thanks to a fast and sensitive comparator, a detection threshold for avalanche events of less than 100 mV is possible. The power consumption of all nine channels is about 250 mW in total. This gating chip is used to characterize the integrated SPADs. A photon detection probability of around 50% at 9.9 V excess bias and for a wavelength of 635 nm is found.

Fast active quenching of single-photon avalanche diodes (SPADs) is important to reduce the afterpulsing probability (APP). An option to reduce the reaction time of electronics to a SPAD's avalanche is to design a quencher exploiting bipolar transistors. A quencher in a 0.35 μm CMOS technology with a nominal supply voltage of 3.3 V, which operated with excess bias voltages up to 6.6 V, was re-designed accordingly. In the new 0.35 μm pure-silicon BiCMOS quencher, the comparator takes advantage of a bipolar differential amplifier, which additionally gives the head room to increase the width of some CMOS transistors as well. The proposed BiCMOS quencher is able to drive the load of a wire-bonded 184 μm-diameter SPAD, while the CMOS design fails. A comparison, where both chips are measured with a wire-bonded, 34 μm-diameter SPAD, shows that the BiCMOS quencher has a reaction time, which is 330 ps to 1.1 ns faster than that of the CMOS quencher.

This paper presents a CMOS-integrated dot avalanche photodiode (dot-APD) that features a small central n+/p-well hemispherical cathode/p-well structure circularly surrounded by an anode ring. The dot-APD enables wide hemispherical depletion, charge collection from a large volume, and a small multiplication region. These features result in a large light-sensitive area, high responsivity and bandwidth, and exceptionally low junction capacitance. The active area can be further expanded using a multi-dot structure, which is an array of several cathode/p-well dots with a shared anode. Experimental results show that a 5 × 5 multi-dot APD with an active area of 70 μm × 70 μm achieves a bandwidth of 1.8 GHz, a responsivity of 9.7 A/W, and a capacitance of 27 fF. The structure of the multi-dot APD allows for the design of APDs in various sizes that offer high bandwidth and responsivity as an optical detector for various applications while still maintaining a small capacitance.

Being ready-to-detect over a certain portion of time makes the time-gated single-photon avalanche diode (SPAD) an attractive candidate for low-noise photon-counting applications. A careful SPAD noise and performance characterization, however, is critical to avoid time-consuming experimental optimization and redesign iterations for such applications. Here, we present an extensive empirical study of the breakdown voltage, as well as the dark-count and afterpulsing noise mechanisms for a fully integrated time-gated SPAD detector in 0.35-μm CMOS based on experimental data acquired in a dark condition. An “effective” SPAD breakdown voltage is introduced to enable efficient characterization and modeling of the dark-count and afterpulsing probabilities with respect to the excess bias voltage and the gating duration time. The presented breakdown and noise models will allow for accurate modeling and optimization of SPAD-based detector designs, where the SPAD noise can impose severe trade-offs with speed and sensitivity as is shown via an example.

Two types of single-photon avalanche diodes (SPADs) with different diameters are investigated regarding their avalanche behavior. SPAD type A was designed in standard 0.35-µm complementary metal-oxide-semiconductor (CMOS) including a 12-µm thick p- epi-layer with diameters of 50, 100, 200, and 400 µm; and type B was implemented in the high-voltage (HV) line of this process with diameters of 48.2 and 98.2 µm. Each SPAD is wire-bonded to a 0.35-µm CMOS clocked gating chip, which controls charge up to a maximum 6.6-V excess bias, active, and quench phase as well as readout during one clock period. Measurements of the cathode voltage after photon hits at SPAD type A resulted in fall times (80 to 20%) of 10.2 ns for the 50-µm diameter SPAD for an excess bias of 4.2 V and 3.45 ns for the 200-µm diameter device for an excess bias of 4.26 V. For type B, fall times of 8 ns for 48.2-µm diameter and 5.4-V excess bias as well as 2 ns for 98.2-µm diameter and 5.9-V excess bias were determined. In measuring the whole capacitance at the cathode of the SPAD with gating chip connected, the avalanche currents through the detector were calculated. This resulted in peak avalanche currents of, e.g., 1.19 mA for the 100-µm SPAD type A and 1.64 mA for the 98.2-µm SPAD type B for an excess bias of 5 and 4.9 V, respectively.

A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35 μm opto-CMOS process fed at 3.3 V and due to the highly effective integrated pin photodiode it operates at μW. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of −26.0 dBm and −25.5 dBm are achieved, respectively, for λ = 635 nm and λ = 675 nm (BER = 10−9 ) with an energy efficiency of 2 pJ/bit.

After a one-year delay caused by the COVID-19 pandemic, the 8th Regional Symposium on Electrochemistry of South-East Europe was held jointly with the 9th Kurt Schwabe Symposium from July 11-15, 2022 at Graz University of Technology in Austria. This special edition of the jESE contains a collection of articles presented at this meeting. The 5-day event (including Monday’s Satellite Student Symposium) organized by the Association of South-East European Electrochemists (ASEEE) featured 5 plenaries, 15 keynotes, 71 contributed talks and 38 posters and was attended by 152 scientists and researchers from 23 countries.

Iodide based energy storage is a potential candidate to improve performance of hybrid supercapacitors and batteries. Here, the authors revisit the previous understanding and show that electrochemical oxidation of iodide results in solid iodine deposits stabilized by the confinement of nanoporous carbons.

The charging of nanoporous carbon via electrodeposition of solid iodine from iodide-based electrolyte is an efficient and ecofriendly method to produce battery cathodes. Here, the interactions at the carbon/iodine interface from first contact with the aqueous electrolyte to the electrochemical polarization conditions in a hybrid cell are investigated by a combination of in situ and ex situ methods. EQCM investigations confirm the flushing out of water from the pores during iodine formation at the positive electrode. XPS of the carbon surface shows irreversible oxidation at the initial electrolyte immersion and to a larger extent during the first few charge/discharge cycles. This leads to the creation of functional groups at the surface while further reactive sites are consumed by iodine, causing a kind of passivation during a stable cycling regime. Two sources of carbon electrode structural modifications during iodine formation in the nanopores have been revealed by in situ Raman spectroscopy, (i) charge transfer and (ii) mechanical strain, both causing reversible changes and thus preventing performance deterioration during the long-term cycling of energy storage devices that use iodine-charged carbon electrodes.

Ionic association in highly concentrated electrolytes hinders the rate performance of batteries and supercapacitors. Herein, an ecofriendly water‐in‐salt electrolyte consisting of choline chloride is proposed. The diffusivity, ionic conductivity and dissociation of water‐in‐choline salt are compared with those of water‐in‐LiTFSI electrolytes, revealing a far better dissociation of the choline salt. The electrochemical studies reveal that ion penetration into the nanoporous carbon electrode is controlled by the hydration shell of the ions and by ion‐pairing at high concentrations. Due to strong lithium hydration in water‐in‐LiTFSI, the positive and negative electrodes exhibit a disparity of the electric double‐layer (EDL) capacitance. For water‐in‐choline chloride, on the contrary, better dissociation leads to facile EDL charging and a similar capacitance at two polarities. Further, battery‐like electrodes are produced via electrodeposition of iodine in carbon electrode. The iodine‐charged battery electrode is then coupled with a carbon‐based EDL electrode in 25 mol kg−1 choline chloride to realize a hybrid capacitor. This device demonstrates constant energy efficiency for 20 000 galvanostatic charge/discharge cycles at a specific current of 1 A g−1 up to 1.6 V. Suppressed polyiodides shuttling due to a shortage of free water in the water‐in‐choline chloride makes it an electrolyte of choice for future hybrid energy storage.

An amendment to this paper has been published and can be accessed via a link at the top of the paper.

Hybrid electrochemical capacitors have emerged as attractive energy storage option, which perfectly fill the gap between electric double-layer capacitors (EDLCs) and batteries, combining in one device the high power of the former and the high energy of the latter. We show that the charging characteristics of the positive carbon electrode are transformed to behave like a battery operating at nearly constant potential after it is polarized in aqueous iodide electrolyte (1 mol L−1 NaI). Thermogravimetric analysis of the positive carbon electrode confirms the decomposition of iodides trapped inside the carbon pores in a wide temperature range from 190 °C to 425 °C, while Raman spectra of the positive electrode show characteristic peaks of I3− and I5− at 110 and 160 cm−1, respectively. After entrapment of polyiodides in the carbon pores by polarization in 1 mol L−1 NaI, the positive electrode retains the battery-like behavior in another cell, where it is coupled with a carbon-based negative electrode in aqueous NaNO3 electrolyte without any redox species. This new cell (the iodide-ion capacitor) demonstrates the charging characteristics of a hybrid capacitor with capacitance values comparable to the one using 1 mol L−1 NaI. The constant capacitance profile of the new hybrid cell in aqueous NaNO3 for 5000 galvanostatic charge/discharge cycles at 0.5 A g−1 shows that iodide species are confined to the positive battery-like electrode exhibiting negligible potential decay during self-discharge tests, and their shuttling to the negative electrode is prevented in this system.

CD44, a transmembrane receptor reported to be involved in various cellular functions, is overexpressed in several cancer types and supposed to be involved in the initiation, progression and prognosis of these cancers. Since the sequence of events following the blockage of the CD44-HA interaction has not yet been studied in detail, we profiled xenograft tumors by RNA Sequencing to elucidate the mode of action of the anti-CD44 antibody RG7356. Analysis of tumor and host gene-expression profiles led us to the hypothesis that treatment with RG7356 antibody leads to an activation of the immune system. Using cytokine measurements we further show that this activation involves the secretion of chemo-attractants necessary for the recruitment of immune cells (i.e. macrophages) to the tumor site. We finally provide evidence for antibody-dependent cellular phagocytosis (ADCP) of the malignant cells by macrophages.