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In this article, we explore different device and standard cell architectures for scaling the Germanium fin field-effect transistor (FinFET) and nanosheet (NS) at the sub-5-nm node. It is demonstrated that the Germanium device provides approximately 70% improvement in drive current and $3.4\times $ less device resistance. The main concern for Germanium devices remains the high leakage current due to the gate-induced drain leakage, which limits their usage to high-speed applications. Overall, Germanium devices require fewer boosters than silicon to scale beyond the 5-nm node. Contact resistivity is found to be a critical knob for Germanium and it can be relaxed to 3e $- 9\,\,\Omega $ -cm2 to meet the power and performance targets for the sub-5-nm node. Moving to the NS helps in relaxing this constraint further.

The NEREID project (“NanoElectronics Roadmap for Europe: Identification and Dissemination”) is dedicated to mapping the future of European Nanoelectronics. NEREID’s objective is to develop a medium and long term roadmap for the European nanoelectronics industry, starting from the needs of applications to address societal challenges and leveraging the strengths of the European eco-system. The roadmap will also identify promising novel nanoelectronic technologies, based on the advanced concepts developed by Research Centres and Universities, as well as identification of potential bottlenecks along the innovation (value) chain. Industry applications include Energy, Automotive, Medical/Life Science, Security, loT, Mobile Convergence and Digital Manufacturing. The NEREID roadmap covers Advanced Logic and Connectivity, Functional Diversification (Smart Sensors, Smart Energy and Energy for Autonomous Systems), Beyond-CMOS, Heterogeneous Integration and System Design as well as Equipment, Materials and Manufacturing Science. This article gives an overview of the roadmap’s structure and content., Thanks are extended to the support of the EU, which has been funded the NEREID project as a Cooperation and Support action for three years from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 685559.

2-D material FETs hold the promise of excellent gate control, but the impact of nonidealities on their performance remains poorly understood. This is because of the need, so far, to use computationally intensive nonequilibrium Green’s function (NEGF) simulations. Here, we therefore use a semiclassical model to investigate the role of nonidealities in the scaling of back-gated (BG) and top-gated (TG) monolayer MoS2 FETs. We verify the electrostatics and transport of the semiclassical model with density functional theory-based NEGF simulations and calibrate nonidealities, such as interface traps ( ${D}_{\textsf {it}}$ ) and Schottky contact barrier height ( $\phi _{\textsf {SB}}$ ) to experimental monolayer and bilayer MoS2 FETs. We find that among the nonidealities, ${D}_{\textsf {it}}$ has the strongest subthreshold swing impact with 70 mV/dec obtainable in BG devices for a ${D}_{\textsf {it}}$ of $5\times {10}^{11}$ cm−2eV $^{-1}$ , an equivalent oxide thickness (EOT) of 1 nm, and a channel length ( ${L}_{\textsf {ch}}$ ) of 5 nm. For scaled EOT, $\phi _{\textsf {SB}}$ only strongly impacts ${I}_{ \mathrm{\scriptscriptstyle ON}}$ for the TG case, as the overlapping gate thins the Schottky barriers in the BG case. We show in TG devices that a spacer of only 5 nm results in a 1000-fold drop in ${I}_{ \mathrm{\scriptscriptstyle ON}}$ because of the nonidealities. We propose positive spacer oxide charge as a solution and show that a charge density of above 1013 cm−2 is required to fully recover the device performance.

Dopant pockets in combination with a III–V heterostructure have become a staple in simulations of tunnel field-effect transistors (TFET) to achieve acceptable on-currents ( ${I} _{\mathrm{ ON}}$ ) and to break the ${I} _{\mathrm{ ON}}$ -subthreshold swing trade-off in pTFETs. Questions on the scalability and variability of these dopant pockets remain, however. We therefore propose an alternative concept using two opposite sheet charges at the tunnel junction that are realized by exploiting different bonding types. With fully quantum mechanical 30-band k.p-based simulations, we investigate two configurations that exhibit such sheet charges both at the device level and in a ring-oscillator: a lattice-matched GaAs-Ge-GaAs heterostructure TFET and a homostructure InGaAs TFET. By comparing to pocketed broken gap GaSb-InAs TFETs, we show that built-in sheet charge is a valid alternative for both nTFET and pTFET, with the prospect of lower variability and better scalability.

In this paper, lateral gate-all-around nano-sheet transistors (NSH-FETs) are explored from intrinsic performance to dc and ring oscillator (RO) benchmark compared with FinFETs and nanowire transistors (NW-FETs) for sub-7-nm node. The band structure calculated technology computer aided design results show comparable intrinsic performance to FinFETs at same channel cross section. On top of that, dc and RO are evaluated by taking into account electrostatics, parasitic components, and layout configurations. The NSH-FETs show an advantage in drive current with the NSH width but their RO performance is limited by the device capacitance. The multiple narrow NSH-FET shows ~5% higher drive current compared to the NW-FET at similar subthreshold swing, allowing heavier capacitive loaded circuit. In addition, NSH-FETs can provide the device design freedom from aggressive fin pitch scaling.

In recent CMOS technology, extreme shrinking of contact area at source/drain regions raises serious concerns of high metal/semiconductor contact resistance. Confronting this problem, we introduce a precontact amorphization implantation plus Ti silicidation technique (PCAI + TiSi x ) and achieve ultralow contact resistivity ( $\rho _{c}$ ) of (1.3 – 1.5) $\times 10^{-9} ~\Omega \cdot \text {cm}^{2}$ on Si:P. This PCAI + TiSi x technique utilizes light amorphization (low-energy implantation), thin Ti and TiSi x film, and moderate thermal budget (500 °C –550 °C): these features are compatible with modern CMOS manufacturing. Moreover, the PCAI + TiSi x -induced $\rho _{c}$ reduction is proved universal on both n- and p-Si. With additional characterizations, we find that the silicidation-induced $\rho _{c}$ variation is not merely a Schottky barrier height tuning effect. The electrical and physical characterizations suggest that the low $\rho _{c}$ is strongly correlated with the formation of interfacial TiSi x crystallites between amorphous TiSi alloy and Si.

We have measured the low-frequency 1/ ${f}$ noise of Si0.55Ge0.45 ${p}$ MOSFETs with a Si capping layer and SiO2/HfO2/TiN gate stack as a function of frequency, gate voltage, and temperature (100–440 K). The magnitude of the excess drain voltage noise power spectral density ( $\textit{S}_{ {vd}}$ ) is unaffected by negative-bias-temperature stress (NBTS) for temperatures below ~250 K, but increases significantly at higher temperatures. The noise is described well by the Dutta-Horn model before and after NBTS. The noise at higher measuring temperatures is attributed primarily to oxygen-vacancy and hydrogen-related defects in the SiO2 and HfO2 layers. At lower measuring temperatures, the noise also appears to be affected strongly by hydrogen-dopant interactions in the SiGe layer of the device.

In this paper, we have developed a straightforward MOS admittance-based technique for defect density extraction, utilizing analytical equations for MOS capacitors with border traps (BTs). We show that these equations can provide an efficient technique to obtain the BT density directly from the measured data without any requirement of numerically involved techniques. This is demonstrated by applying the methodology on measured C–V data from Al2O3- and HfO2-based MOSCAPs. The extracted densities show less than 5% difference from the values extracted using the fitting-based methodology used in previous reports. We show that, due to the analytical nature of these equations, they can be used to understand the impact of each defect parameter on the admittance. We extensively prove the applicability of the analytical solution for a very wide range of parameter values. In addition, we lay out a methodology for defect density extraction, which can be easily automated for the characterization of large scale data sets of high-k dielectrics on III–V MOS devices.

We examine the power-performance variability of a projected sub-5-nm GaAsSb/InGaAs vertical tunnel FET considering various process control tolerances in the state-of-the-art device integration and propose countermeasures in device design. Nominal and three-sigma-corner device characteristics generated in quantum-mechanical/TCAD simulations are used to calibrate a semiempirical compact model, based on which the nominal and variability-inclusive energy-delay landscapes are extracted from ring-oscillator circuit simulations at sub-500-mV supply voltages. Variations in four parameters are identified as of major impact on the worst-case speed loss and iso-speed energy penalty: dopant pocket thickness, gate work function, hetero-band offset, and body thickness (in descending order). Variability-resilient device options are explored against pocket thickness variation, including: 1) pocket desensitization with increased thickness and reduced doping concentration and 2) broken-gap tunnel FET with a negative effective band gap. Reengineered devices achieve

The effective bandgap for heterojunction band-to-band tunneling ( $ {{E}}_{{\text {g,eff}}}$ ) is a crucial design parameter for a heterojunction tunneling FET (TFET). However, there is significant uncertainty on $ {{E}}_{{\text {g,eff}}}$ , especially for In0.53Ga0.47As/ GaAs0.5Sb0.5. This makes the prediction of TFET performance difficult. We calibrate $ {{E}}_{{\text {g,eff}}}$ by fabricating heterojunction p+/i/n+ diodes, comparing the simulated and the measured current–voltage and capacitance–voltage curves, while taking $ {{E}}_{{\text {g,eff}}}$ as a fitting parameter. Our calibration significantly reduces the uncertainty on $ {{E}}_{{\text {g,eff}}}$ compared with the range found in the literature. The comparison with the previous work on highly doped heterojunction diodes suggests that dopant-dependent bandgap narrowing reduces $ {{E}}_{{\text {g,eff}}}$ and therefore significantly impacts the performance of highly doped TFET.

The electrostatic and leakage effects of extended defects on Si and Ge MOSFETs are investigated. A technology computer-aided design model of extended defects is developed based upon measured device electrical properties. A single extended defect is introduced into simulated 2-D planar and 3-D FinFET structures. It is found that a 2-D extended defect is a source of variability in planar transistors, with the electrical effects depending on its position along the channel. A 2-D extended defect increases the threshold voltage and subthreshold swing when it is in the channel and increases the leakage current when it is in the drain. The dislocation effect on transistor characteristics increases with decreasing transistor width. The effect is less pronounced in FinFETs due to the well-controlled electrostatics and the small dislocation volume.

Strain can strongly impact the performance of III-V tunnel field-effect transistors (TFETs). However, previous studies on homostructure TFETs have found an increase in ON-current to be accompanied with a degradation of subthreshold swing. We perform 30-band quantum mechanical simulations of staggered heterostructure p-n-i-n TFETs submitted to uniaxial and biaxial uniform stress and find the origin of the subthreshold degradation to be a reduction of the density of states in the strained case. We apply an alternative configuration including a lowly doped pocket in the source, which allows to take full benefit of the strain-induced increase in ON-current.

In this paper, a new scheme called diffusion and gate replacement (D&GR) metal-inserted polysilicon integration is demonstrated. The CMOS flow allows controlling the gate height asymmetry between the nMOS and the pMOS by driving the work function shifter directly into the high- $k$ , and then by removing the dopant source (dummy doped metal gate) and depositing a fresh TiN metal gate. Although the integration flow is compatible with a standard 45-/28-nm technological node, it has been specifically designed to be compatible with dynamic random access memory peripheral applications or other emerging memories (embedded applications). A material down-selection is done (TiN/Mg/TiN gate-stack for nMOS and Al2O3 capping layer for pMOS), and it is demonstrated that a process window exists and guarantees enough work function lowering without compromising the electrical parameters (electrical oxide thickness, mobility, subthreshold slope, and gate leakage). Regarding the CMOS integration, it is shown that an nMOS-first integration is preferable, and that there is no contamination issue of the pMOS work function shifter (in this case, Al2O3) on the nMOS side. Finally, CMOS device performance is on par with the non-D&GR baseline, validating the integration flow.

A simple analytical low-field electron mobility model to be employed for technology computer-aided design of thin-body MOSFETs based on III-V compound semiconductors is presented. The scattering sources accounted for in the model are Coulomb centers, lattice vibrations (i.e., phonons), and surface roughness. The dependence of the thin-body effective thickness on the transverse electric field is calculated through 1-D Schrodinger–Poisson numerical simulations and is introduced in the model by means of an appropriate analytical function. Then, the free-electron density distribution is determined by considering both quantization effects and oxide–semiconductor interface traps. The model is calibrated on the experimental data collected on In0.53Ga0.47As-on-InP thin-body MOSFETs featuring body thicknesses as low as 5 nm. In particular, the model accurately reproduces $C_{G}$ – $V_{\mathrm{ GS}}$ characteristics, effective mobility against inversion layer charge plots, and $I_{\mathrm{ DS}}$ – $V_{\mathrm{ GS}}$ curves at low $V_{\mathrm{ DS}}$ .

The gate-stack quality of planar MOSFETs fabricated in Ge-on-Si substrates and passivated by a GeO x interfacial layer is evaluated by low-frequency noise analysis. It is shown that for both n- and p-channel transistors predominantly 1/ $f^{\gamma }$ noise ( $\gamma \sim 1$ ) has been observed, which originates from number and correlated mobility fluctuations. The oxide trap density and mobility scattering coefficient derived from the input-referred voltage noise power spectral density are demonstrated to be significantly higher for nMOSFETs than for pMOSFETs with the same gate-stack, which explains the low electron mobility.

I. Introduction The growing demand for power efficient devices has accelerated the research into the use of the tunnel field-effect transistor (TFET) in future ultra-low power applications because of its promising potential for sub-60 mV/dec subthreshold swing achieved through quantum mechanical band-to-band tunneling (BTBT) [1]-[3]. Unfortunately, a significant gap between theoretical predictions and experiments remains to be bridged [2]. Considerable efforts are being made to develop models for some of the main causes of suboptimal TFET performance such as trap-assisted tunneling (TAT) [4], [5], phonon-assisted tunneling (PAT) [6], and Auger generated leakage currents [7]. However, aside from qualitative analyses [8] and purely predictive work on the device impact of tunneling transitions involving high-doping induced band-tails states in InSb nanowire TFETs [9] and 2D-TFETs [10], no attempts have been made to calibrate these contributions. This work aims to fill this gap by developing and calibrating an approximate ballistic semi-classical (SC) model for high-doping induced band-tails using the experimental I-V data of In0.53Ga0.47As p-i-n Esaki diodes [11]. The hypothesis is posited that the mismatch between measurement and simulation in the negative differential resistance regime (see Fig. 1), which cannot be explained by SC TAT models, is caused by ballistic band-tails tunneling. The calibration thus gives an upper limit to the band-tails current. Lastly, the impact of band-tails on the performance of a p-n-i-n TFET is investigated.

For the first time, two different types of electron traps are clearly identified in Ge nFETs with Type-A controlled by the HfO 2 layer thickness and Type-B by the Si growth induced Ge segregation. Only Type-B are responsible for mobility degradation and they do not saturate with stress time, while the opposite applies to Type A. A PBTI model is proposed and validated for the long term prediction.

© 2018 Author(s). In the quantum mechanical simulation of exploratory semiconductor devices, continuum methods based on a k ⋅p/envelope function model have the potential to significantly reduce the computational burden compared to prevalent atomistic methods. However, full-zone k ⋅p/envelope function simulation approaches are scarce and existing implementations are not self-consistent with the calculation of the electrostatic potential due to the lack of a stable procedure and a proper normalization of the multi-band envelope functions. Here, we therefore present a self-consistent procedure based on a full-zone spectral k ⋅p/envelope function band structure model. First, we develop a proper normalization for the multi-band envelope functions in the presence of transmitting boundary conditions. This enables the calculation of the free carrier densities. Next, we construct a procedure to obtain self-consistency of the carrier densities with the electrostatic potential. This procedure is stabilized with an adaptive scheme that relies on the solution of Poisson’s equation in the Gummel form, combined with successive underrelaxation. Finally, we apply our procedure to homostructure In 0.53Ga 0.47As tunnel field-effect transistors (TFETs) and staggered heterostructure GaAs 0.5Sb 0.5/In 0.53Ga 0.47As TFETs and show the importance of self-consistency on the device predictions for scaled dimensions. ispartof: JOURNAL OF APPLIED PHYSICS vol:124 issue:20 status: published

Systematic experimental studies on phosphorus diffusion from phosphosilicate glass into the p-type bulk Si (100) substrate with different capping barrier layer thicknesses have been conducted. In both 2- and 5-nm phosphosilicate glass conditions, a thicker SiO2 cap showed a lower sheet resistance and a higher retained phosphorus dose in the Si substrate after 1050 °C 4 s rapid thermal annealing as drive-in annealing. However, the sheet resistance of 2-nm phosphosilicate glass with a 10-nm SiO2 cap was lower than that of 5-nm phosphosilicate glass with a 3-nm SiO2 cap due to a higher retained phosphorus dose in the Si substrate. For a higher retained phosphorus dose in the Si substrate using fixed total thickness, 2-nm phosphosilicate glass with 6-nm SiO2 cap is better than 5-nm phosphosilicate glass with 3-nm SiO2 cap since prevention of phosphorus out-diffusion during the drive-in annealing is more important than the total phosphorus dose in phosphosilicate glass. Next, SiO2 cap thickness on 2-nm phosphosilicate glass was split to understand the role of the SiO2 capping layer in detail for scaled devices. 3-nm SiO2 cap could not prevent out-diffusion during the drive-in annealing, and it showed much higher sheet resistance and lower retained phosphorus dose in the Si substrate. The highest retained phosphorus dose in the Si substrate was observed for 6-nm SiO2 cap and resulted in 1.8 × 1014 atoms/cm2 retained phosphorus dose with 96% activation level after 1050 °C 4 s rapid thermal annealing. Thicker SiO2 caps than 6 nm were not beneficial since 10-nm SiO2 cap showed a higher sheet resistance value as well as lower phosphorus activation level (82%) compared to 6-nm SiO2 cap even though both the process conditions showed same phosphorus profiles after the drive-in annealing. That sheet resistance increase with 10-nm SiO2 cap could be caused by heterogeneous surface formation on the Si substrate with a prolonged SiO2 atomic layer deposition process.

The effective bandgap is a crucial design parameter of heterojunction tunneling field-effect transistors. In this letter, we demonstrate a method to measure the effective bandgap directly from the band-to-band tunneling current of a heterojunction Esaki diode, of which we only require knowledge of the electrostatic potential profile. The method is based on a characteristic exponentially increasing current with forward bias, caused by sharp energy filtering at cryogenic temperature. We apply this method experimentally to a n+In0.53Ga0.47As/pGaAs(0.5)Sb(0.5) Esaki diode and define requirements to apply it to other heterojunctions. ispartof: Applied Physics Letters vol:107 issue:7 pages:1-4 status: published

The trap-assisted tunneling (TAT) current in tunnel field-effect transistors (TFETs) is one of the crucial factors degrading the sub-60 mV/dec sub-threshold swing. To correctly predict the TAT currents, an accurate description of the trap is required. Since electric fields in TFETs typically reach beyond 10(6) V/cm, there is a need to quantify the impact of such high field on the traps. We use a quantum mechanical implementation based on the modified transfer matrix method to obtain the trap energy level. We present the qualitative impact of electric field on different trap configurations, locations, and host materials, including both semiconductors and oxides. We determine that there is an electric-field related trap level shift and level broadening. We find that these electric-field induced quantum effects can enhance the trap emission rates. Published by AIP Publishing.