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An integrated optical isolator is a crucial part of photonic integrated circuits (PICs). Existing optical isolators, predominantly based on the silicon-on-insulator (SOI) platform, face challenges in integrating with active devices. We propose a broadband, compact TM mode Mach–Zehnder optical isolator based on InP-on-insulator platforms. We designed two distinct magneto-optical waveguide structures, employing different methods for bonding Ce:YIG and InP, namely O2 plasma surface activation direct wafer bonding and DVS-benzocyclobutene (BCB) adhesive bonding. Detailed calculations and optimizations were conducted to enhance their non-reciprocal phase shift (NRPS). At a wavelength of 1550 nm, the direct-bonded waveguide structure achieved a 30 dB bandwidth of 72 nm with a length difference of 0.256 µm. The effects of waveguide arm length, fabrication accuracy, and dimensional errors on the device performance are discussed. Additionally, manufacturing tolerances for three types of lithographic processes were calculated, serving as references for practical manufacturing purposes. [ABSTRACT FROM AUTHOR]

The availability of thin-film lithium niobate on insulator (LNOI) and advances in processing have led to the emergence of fully integrated LiNbO3 electro-optic devices. Yet to date, LiNbO3 photonic integrated circuits have mostly been fabricated using non-standard etching techniques and partially etched waveguides, that lack the reproducibility achieved in silicon photonics. Widespread application of thin-film LiNbO3 requires a reliable solution with precise lithographic control. Here we demonstrate a heterogeneously integrated LiNbO3 photonic platform employing wafer-scale bonding of thin-film LiNbO3 to silicon nitride (Si3N4) photonic integrated circuits. The platform maintains the low propagation loss (<0.1 dB/cm) and efficient fiber-to-chip coupling (<2.5 dB per facet) of the Si3N4 waveguides and provides a link between passive Si3N4 circuits and electro-optic components with adiabatic mode converters experiencing insertion losses below 0.1 dB. Using this approach we demonstrate several key applications, thus providing a scalable, foundry-ready solution to complex LiNbO3 integrated photonic circuits. Lithium niobate plays an important role in integrated photonics, but its widespread application requires a reliable solution. Here, the authors present a wafer-scale approach to LNOI integration via wafer bonding to silicon nitride PICs. [ABSTRACT FROM AUTHOR]

We employed creatively cold isostatic pressing technology to develop room-temperature bonding of Si–Si using 200-nm Au layers, which the ultra-high pressure was transmitted equally to Si–Si bonding samples by direct contact with the pressure medium during the cold isostatic pressing. We explored the influence of bonding pressure on the bonding rate. It was found that ultra-dense interconnects can be realized and the bonding rate increased with the increase of bonding pressure, which was attributed to the increased metal bond density. With the help of an excellent plastic deformation capacity of Au layers and ultra-high uniform isostatic pressing technology, a bonding rate of the whole 2-in. wafer reached 96.37% observed by scanning acoustic microscope. Simultaneously, in accord with the experiment results, we proposed the bonding mechanism model and discussed it in detail. Furthermore, taking laser lift-off as the front-end process, GaN HEMT devices were successfully transferred from sapphire to Si substrates with this method. Bonded GaN devices on Si substrate have been characterized. The dc characteristics showed an increase in the electrical performance of the GaN HEMT with maximum current density changing from 254 to 290 mA/mm. With the advantages of room-temperature bonding and without surface treatment, the technique was available in high-quality integration of chips. This room-temperature bonding via an ultra-high isostatic pressing strategy may inspire the development of a heterogeneous interconnection architecture and functional integrated circuits delivering a monolithic-like performance in the future hyper-scaling era. [ABSTRACT FROM AUTHOR]

Featured Application: Compact lasers integrated onto SOI for optical communications. The tremendous demand for low-cost, low-consumption and high-capacity optical transmitters in data centers challenges the current InP-photonics platform. The use of silicon (Si) photonics platform to fabricate photonic integrated circuits (PICs) is a promising approach for low-cost large-scale fabrication considering the CMOS-technology maturity and scalability. However, Si itself cannot provide an efficient emitting light source due to its indirect bandgap. Therefore, the integration of III-V semiconductors on Si wafers allows us to benefit from the III-V emitting properties combined with benefits offered by the Si photonics platform. Direct epitaxy of InP-based materials on 300 mm Si wafers is the most promising approach to reduce the costs. However, the differences between InP and Si in terms of lattice mismatch, thermal coefficients and polarity inducing defects are challenging issues to overcome. III-V/Si hetero-integration platform by wafer-bonding is the most mature integration scheme. However, no additional epitaxial regrowth steps are implemented after the bonding step. Considering the much larger epitaxial toolkit available in the conventional monolithic InP platform, where several epitaxial steps are often implemented, this represents a significant limitation. In this paper, we review an advanced integration scheme of AlGaInAs-based laser sources on Si wafers by bonding a thin InP seed on which further regrowth steps are implemented. A 3 µm-thick AlGaInAs-based MutiQuantum Wells (MQW) laser structure was grown onto on InP-SiO2/Si (InPoSi) wafer and compared to the same structure grown on InP wafer as a reference. The 400 ppm thermal strain on the structure grown on InPoSi, induced by the difference of coefficient of thermal expansion between InP and Si, was assessed at growth temperature. We also showed that this structure demonstrates laser performance similar to the ones obtained for the same structure grown on InP. Therefore, no material degradation was observed in spite of the thermal strain. Then, we developed the Selective Area Growth (SAG) technique to grow multi-wavelength laser sources from a single growth step on InPoSi. A 155 nm-wide spectral range from 1515 nm to 1670 nm was achieved. Furthermore, an AlGaInAs MQW-based laser source was successfully grown on InP-SOI wafers and efficiently coupled to Si-photonic DBR cavities. Altogether, the regrowth on InP-SOI wafers holds great promises to combine the best from the III-V monolithic platform combined with the possibilities offered by the Si photonics circuitry via efficient light-coupling. [ABSTRACT FROM AUTHOR]

III–V materials, such as InGaAs and InP, are highly attractive for high-performance electronics and optoelectronics owning to their high carrier mobilities and potential for bandgap engineering. Integration on silicon substrates, however, is a key requirement to enable widespread adoption of these materials. In this work, direct wafer bonding (DWB) of III–V materials is explored as a low-temperature enabling technology for Si integration. For high-performance logic and RF electronics, DWB is compared to competing integration technologies and is shown to exhibit higher device performance due to its relatively low process complexity and thermal impact (~300 °C). Due to the low thermal impact of DWB, it is also uniquely suitable for 3-D integration, i.e., vertical stacking of multiple functional layers. III–V optoelectronics are attractive in such 3-D stacks, where they can enable high-efficiency tunable lasers together with Si photonics integrated circuits. DWB is here compared to selective epitaxy as an integration route for InP-on-Si microdisk lasers. Plasmonics are explored as well, allowing scaling of integrated III–V photonic devices beyond the diffraction limit of light. The results of this work show that DWB is a highly promising integration route for III–V materials for both electronics and optoelectronics applications. [ABSTRACT FROM AUTHOR]

During Through Silicon Via (TSV) wafer backside thinning process, excessive surface stress will cause undue warpage or fracture of wafer in subsequent de-bonding step, and further impair the precision of following wafer stacking and packaging. Therefore, it is considerable to investigate the evolution mechanism of wafer stress and how to control it in backside thinning process. Aiming at the above problem, a calculation method is proposed in this paper to characterize surface stress of TSV wafer in a bonding structure, and the method has been confirmed by micro-Raman spectroscopy; Then, based on the method, the change of stress in TSV wafer during a whole backside thinning process is described, and the formation and evolution mechanism of surface stress is analyzed; At last, the stress control performance and corresponding mechanism explanation under different process parameters are demonstrated, and the optimal process condition is selected, which can release more than 80 percent of generated stress. In summary, this work can be regarded as a reference in three-dimension integrated circuit (3D IC) industry to select proper thinning conditions in order to obtain an optimized stress relief performance. [ABSTRACT FROM AUTHOR]

The article discusses the potential of the wafer bonding technology for the achievement of improved accuracy for bond alignment. Topics include the increase chip performance offered by three-dimensional integrated circuit (3D-IC), the establishment of some 3D-IC in the middle of the fabrication process, and the transformation of the bonding materials to achieve the successful fusion bonding.

A new 3-D integration concept based on reconfigured wafer-to-wafer stacking is proposed. Using reconfigured wafer-to-wafer 3-D integration, many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer, which is called a reconfigured wafer. In addition, the KGDs on the reconfigured wafer can be transferred and bonded to another target wafer at the wafer level. The alignment accuracy is within 1 \mum when 3\,\times\,3-, 5\,\times\,5-, 4\,\times\,9,- or 10\,\times\,10-mm^2 chips are employed. To 3-D stack many KGDs in a batch process, we developed and employed a self-assembly multichip bonder. KGDs with 20-\mum-pitch Cu–SnAg microbumps covered with a nonconductive film as a preapplied underfill material on their top surface were self-assembled right-side up, and then transferred to the corresponding target interposer wafer upside down. The resulting daisy chain with 500 Cu–SnAg microbumps exhibited ohmic contacts, and the resistance of \sim40~m\Omega/bump was sufficiently low for 3-D large-scale integration application. [ABSTRACT FROM AUTHOR]

A new concept of semiconductor wafer bonding, mediated by optical wavelength conversion materials, is proposed and demonstrated. The fabrication scheme provides simultaneous bond formation and interfacial function generation, leading to efficient device production. Wavelength-converting functionalized semiconductor interfacial engineering is realized by utilizing an adhesive viscous organic matrix with embedded fluorescent particles. The bonding is carried out in ambient air at room temperature and therefore provides a cost advantage with regard to device manufacturing. Distinct wavelength conversion, from ultraviolet into visible, and high mechanical stabilities and electrical conductivities in the bonded interfaces are verified, demonstrating their versatility for practical applications. This bonding and interfacial scheme can improve the performance and structural flexibility of optoelectronic devices, such as solar cells, by allowing the spectral light incidence suitable for each photovoltaic material, and photonic integrated circuits, by delivering the respective preferred frequencies to the optical amplifier, modulator, waveguide, and detector materials. [ABSTRACT FROM AUTHOR]