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Dead-time is the most important disturbance in a voltage-source inverter's operation. It introduces low-order harmonics at the inverter's output voltage. To compensate for the dead-time effects in three-phase grid-tied inverters, this paper proposes a Linear Quadratic Gaussian (LQG) multivariable control approach. The LQG multivariable control is known as a robust control approach while provides a high band-width for the closed-loop system. Therefore, it promises significant attenuations in the dead-time introduced harmonics. To achieve a high performance, we run the three-phase grid-tied inverter in the current-controlled mode. Based on the nominal multivariable model derived for the three-phase grid-tied inverter in a synchronous reference frame, the LQG controller is composed such that the closed-loop system exhibits robust stability while attenuates disturbances significantly. The dead-time introduced harmonics produce disturbances in the synchronous reference frame with the highest frequencies. This is the reason for considering the dead-time as the most important disturbance in an inverter's operation. For an experimental set-up manufactured for the three-phase grid-tied inverter, we developed a detailed model in MATLAB/Simulink. It is employed for the performance verifications of designed LQG controller. Extensive results are presented for different important scenarios, based on which, the excellent performance of proposed approach is proven. In fact, by employing the proposed approach, the dead-time introduced harmonics are significantly attenuated such that a Total Harmonics Distortions (THD) of about 5% is achieved for the injected currents to grid which meets the IEEE 1547 standard. [ABSTRACT FROM AUTHOR]

A fully digital algorithm to shape the spectrum of dead-time distortion in power inverters is presented. Dead-time is required to avoid short circuits of the power source by the legs of a power inverter due to the finite turn-onand turn-offtimes of the switches. Dead-time modifies the pulsewidths of the pulsewidth modulated (PWM) signal causing high harmonic distortion. The proposed approach is based on the time-to-digital conversion of the pulsewidths at the output of the power stage and does not require to measure the sign of the current, which is the preferred approach for dead-time compensation algorithms. The effect of the parasitic capacitance of the switching device that distorts the switching waveform is also analyzed and corrected. Furthermore, the quantization noise produced by digital PWM is also reduced by the proposed approach and has a minimal computational cost. Hardware-in-the-loop simulations are provided to show the effectiveness of the proposed approach, and experimental results using an H-bridge voltage-source inverter are included. A minimum total harmonic distortion plus noise (THD+N) of $\text{0.027}\%$ was achieved for a $\text{1}$ -kHz input driving an inductive load. [ABSTRACT FROM AUTHOR]

Inverter dead-time is known to make open-loop induction motor drives oscillatory, while operating at light-loads in particular. While dead-time compensation schemes exist, precise compensation of the same is often challenging as it involves factors such as device and driver delays and switching transition times, which are difficult to be quantified accurately. Hence, the effect of dead-time could be under or overcompensated. This paper presents a comprehensive analysis of the impact of such undercompensation and overcompensation on the stability of a 100-kW induction motor drive, along with experimental investigations of the same. The effects of undercompensation and overcompensation on the inverter output voltage are analyzed on a switching-cycle average basis. Further, small-signal models are proposed for an open-loop drive, when it is undercompensated and overcompensated. Stability analysis of the above motor drive is reported, which predicts oscillatory behavior with both under and overcompensation, over certain fundamental frequency ranges, respectively. Further, two different types of oscillatory behavior, characterized by different oscillating frequencies, are observed for the cases of under and overcompensation. The analyses are supported by simulations. Experimental investigations carried out also support the analyses and simulation results. [ABSTRACT FROM AUTHOR]

The effect of inverter dead time on the inverter output voltage is well studied in the literature. This paper studies the effect of the dead time on the inverter input current. An expression for the switching-cycle-averaged inverter input current including the dead time effect is derived, which shows the dead time effect to primarily result in a reduction in the average value of the inverter dc input current. The effect of dead time on the input current is incorporated into the dc-link dynamic model of a diode-bridge-rectifier (DBR) fed voltage source inverter (VSI). A switching-cycle-average model of a DBR-VSI-fed induction motor is proposed, which considers the effect of dead time on both the ac output voltage and dc input current of the VSI. The proposed average model is used to study the light-load instability phenomenon in a 100-kW open-loop motor drive. The proposed model is shown to predict the region of oscillatory behavior (i.e., region exhibiting light-load instability) with better accuracy than existing average models. The proposed model also accurately predicts the dc-link voltage swing at such oscillatory operating points. While being comparable in accuracy in predicting the system dynamics, the proposed model is much more computationally efficient than the state-of-the-art switching model. The validity of the proposed average model is also confirmed by experimental measurements on a 100-kW induction motor drive. [ABSTRACT FROM AUTHOR]

In voltage-source inverters (VSIs), dead time is used to prevent shoot-through over switching devices. However, the existence of the dead time will distort the output phase current, which degrades the performance of the inverter as well as influences the common-mode voltage (CMV), particularly in CMV elimination relevant modulation schemes, such as zero-common-mode (CM) pulsewidth modulation (PWM)-based paralleled inverters. In the light of the situation that the normal sampling-based dead-time compensation (DTC) methods are often disturbed by the current ripple, this paper introduces a novel DTC method for the VSI, which can mitigate the impact of the current ripple and improve the accuracy of DTC. The proposed method deduces the real-time current ripple, which can reconstruct the actual trajectory of phase-leg currents, and the peak values corresponding to rising and falling edges for PWM signals can be predicted. In this way, DTC can be implemented based on the direction of relevant instantaneous switching currents and finally improves the accuracy. Especially, the current-ripple-prediction-based DTC can help to improve the CMV distortion caused by the dead time for paralleled inverters with zero-CM PWM. Simulation and experimental results are provided to validate that the proposed method can be applied to different topologies and modulation schemes with good performance. [ABSTRACT FROM AUTHOR]

To reduce the common-mode voltage (CMV) and eliminate the CMV spikes for two-level voltage source inverters (2L-VSIs), an improved model predictive control (MPC) based CMV reduction method is proposed in this paper considering dead-time effects. First, an improved voltage vector (VV) preselection strategy is proposed to reduce the CMV spikes caused by the dead time. Second, a new hybrid VV preselection strategy based on a delay compensation strategy and a modified current sector division strategy is proposed to completely eliminate the CMV spikes. As the proposed hybrid VV preselection based MPC strategy makes full use of the six nonzero VVs of the 2L-VSI, the current total harmonic distortions and ripples are reduced. The simulation and experiments are carried out to verify the effectiveness of the proposed strategy. [ABSTRACT FROM AUTHOR]

Aiming at the reduction of the influence of the dead time setting on power level and efficiency of the inverter of double-sided LCC resonant wireless power transfer (WPT) system, a dead time soft switching optimization method for metal-oxide-semiconductor field-effect transistor (MOSFET) is proposed. At first, the mathematic description of double-sided LCC resonant wireless charging system is established, and the operating mode is analyzed as well, deducing the quantitative characteristic that the secondary side compensation capacitor C2 can be adjusted to ensure that the circuit is inductive. A dead time optimization design method is proposed, contributing to achieving zero-voltage switching (ZVS) of the inverter, which is closely related to the performance of the WPT system. In the end, a prototype is built. The experimental results verify that dead time calculated by this optimized method can ensure the soft switching of the inverter MOSFET and promote the power and efficiency of the WPT. [ABSTRACT FROM AUTHOR]

The objective of this paper is to study the influence of inverter dead-time on steady as well as dynamic operation of an open-loop induction motor drive fed from a voltage source inverter (VSI). Towards this goal, this paper presents a systematic derivation of a dynamic model for an inverter-fed induction motor, incorporating the effect of inverter dead-time, in the synchronously revolving dq reference frame. Simulation results based on this dynamic model bring out the impact of inverter dead-time on both the transient response and steady-state operation of the motor drive. For the purpose of steady-state analysis, the dynamic model of the motor drive is used to derive a steady-state model, which is found to be non-linear. The steady-state model shows that the impact of dead-time can be seen as an additional resistance in the stator circuit, whose value depends on the stator current. Towards precise evaluation of this dead-time equivalent resistance, an analytical expression is proposed for the same in terms of inverter dead-time, switching frequency, modulation index and load impedance. The notion of dead-time equivalent resistance is shown to simplify the solution of the non-linear steady-state model. The analytically evaluated steady-state solutions are validated through numerical simulations and experiments. [ABSTRACT FROM AUTHOR]

In power electronics drive systems, dead time is used to prevent shoot-through over power devices. However, dead time can lead to distortion of ac output voltages and currents. Various compensation methods have been proposed to overcome this drawback. However, most strategies assume the power switches as ideal switches and the transition from ON to OFF or vice versa is infinitely fast. In this paper, effects of inverter snubber and parasitic capacitance to the switching instants are investigated when doing dead-time compensation. A new dead-time compensation method is presented with the capacitance being considered. It is verified that the compensation becomes more accurate and effective for the specific application after the modification. It is also shown that the proposed compensation can make the inverter system stable and robust. This proposed approach is validated by the experimental results. [ABSTRACT FROM AUTHOR]

In this paper, an immune algorithm (IA)-based dead-time elimination PWM control strategy is proposed. For existing dead-time elimination applications, one of the major problems is the dead-time control around the zero-current-crossing points. To deal with this problem, this paper proposes a different PWM control method which first restricts the control sequence to a specified level around the zero-crossing zone. Also, the proposed method can improve the current waveform quality by using the IA approach and three-level control strategy. Compared with conventional dead-time elimination methods, this technique has the features of simple hardware requirement and adaptive control. Moreover, this control strategy effectively eliminates the effect of dead-time, while at the same time significantly reducing the total harmonic distortion of output current and improving the amplitude of output RMS value in different modulation indexes and loads conditions. To verify the analysis, an experimental platform based on DSP and field-programmable gate array is built. The simulation and experimental results are given to demonstrate the effectiveness and feasibility of this new method. [ABSTRACT FROM AUTHOR]

Hysteresis current control is an attractive nonlinear current-control method for voltage source inverters when a fast system response is required. A well-known disadvantage of hysteresis current control is that the system has to operate over a wide switching frequency range. This causes an increase in the switching losses of the system and increases the difficulty in designing the output filter. The recently proposed parabolic current control solves this problem by employing a pair of parabolic carriers as the control band. Through the use of parabolic current control, constant switching frequency can be achieved. In the implementation of parabolic current control, dead time is employed to prevent shoot through of the inverter leg. The employment of dead time impacts the current-tracking precision and the stability range of the parabolic current-control method. Another side effect of using dead time is that the switching frequency deviates from the desired value. In this paper, the effects of dead time on parabolic current control are analyzed, and a compensation method is proposed for voltage source inverters that use parabolic current control. Using the output current direction of the voltage source inverter, a new pair of improved parabolic carriers is derived. As a result, the current error can be well controlled and the effects of dead time can be eliminated. The improvement in the current tracking of the system comes with an added benefit where the duty cycle range is extended. The effectiveness of the proposed dead-time compensation method is experimentally verified by the use of a full-bridge voltage source inverter. [ABSTRACT FROM AUTHOR]

This paper proposes a new method of dead-time effect compensation. The proposed solution is based on additional phase current measurements realized by analog-to-digital converters. These measurements are carried out at the time instants specified by a pulsewidth-modulation (PWM) strategy. This makes it possible to estimate inverter currents at the commutation instants and, finally, to estimate the voltage error caused by dead time. This voltage error is compensated during the next switching period by modification of a reference voltage. The proposed solution can be used to compensate the voltage error in multilevel multiphase voltage source inverters. The experimental research studies were carried out on three-phase two-level and three-level neutral-point-clamped inverters supplying 55- and 160-kW motors, respectively. The results of the experimental investigations are presented in this paper. [ABSTRACT FROM PUBLISHER]

This paper presents an extended electromotive-force-based discrete-time sliding-mode observer (DSMO) for rotor position/speed sensorless control of interior permanent-magnet synchronous machines (IPMSMs). Without using voltage sensors to measure IPMSM terminal voltages, the reference voltages generated by the vector control system are used as inputs for the DSMO. However, due to the inverter dead-time effect, the mismatch between the reference voltages and actual terminal voltages will degrade the performance of DSMO. In this paper, the periodically oscillating rotor position estimation error caused by the dead-time is first analyzed. Then, a dead-time compensation scheme is proposed to mitigate this position estimation error. The proposed DSMO with the dead-time compensation scheme is validated on an IPMSM control system used in heavy-duty, off-road, hybrid, and electric vehicles. [ABSTRACT FROM AUTHOR]

The term dead time refers to a prime safety factor for most power electronic converter topologies, and it is included either in the control software or in the gate/base driver hardware, depending on the application as well as the control requirements. In this paper, the authors present a comprehensive numerical analysis of dead-time effects on the output voltage of a three-level neutral-point-clamped (NPC) inverter. To incorporate the dead-time effect in the output voltage, 3-D models of three-level carrier pulse width modulation (PWM) methods are modified for two dead-time implementations. Closed-form expressions of inverter phase voltage harmonics for phase opposition disposition (POD) PWM are derived based on the double Fourier series approach and modified contour plots. The harmonic spectra from numerical evaluations, simulations, and experiments for natural sampling (NS), symmetrical regular sampling (SRS), and asymmetrical regular sampling (ARS) are compared to validate the mathematical models. In addition, the fundamental voltage with respect to the dead time and the load phase angle is presented based on analytical results and simulation. [ABSTRACT FROM PUBLISHER]

This paper will present a dead-time elimination scheme for a pulsewidth-modulation (PWM)-controlled inverter/ converter. The presented dead-time elimination scheme does not require separated power supplies for freewheeling-current detection of highand low-side power devices. The presented scheme includes the freewheeling-current polarity detection circuit and the PWM control generator without dead time. It will be shown that the presented scheme eliminates the dead time of PWM control for inverter/converter and therefore dramatically improves output voltage loss and current distortion. Experimental results derived from a field-programmable-gate-array-based PWM-controlled inverter are shown to demonstrate the effectiveness. [ABSTRACT FROM AUTHOR]

This paper introduces a combination of two proposed efficiency improvement techniques for a microinverter with current mode control zero-voltage switching output stages. The first technique is dynamic dead-time optimization wherein pulse width modulation dead times are dynamically adjusted as a function of load current. The second method is advanced phase skipping control which maximizes inverter efficiency by controlling power on individual phases depending on the available input power from the photovoltaic source. Neither of the techniques requires any additional circuit components and both can be easily implemented in digital controller firmware. The two techniques were designed and implemented in a 400-W three-phase microinverter prototype. The experimental results validate the theoretical analysis of these techniques and demonstrate that a significant efficiency improvement can be achieved by combining the two proposed control techniques. [ABSTRACT FROM AUTHOR]

A simple parameter-independent online compensation scheme for the dead time and inverter nonlinearity in an interior-permanent-magnet-synchronous-motor drive through waveform analysis is presented. The effectiveness of the proposed scheme is verified through the simulations and experiments using the DSP TMS320F28335. Without requiring any additional hardware, the proposed scheme can effectively compensate the dead time and inverter nonlinearity even in the presence of the parameter uncertainty. [ABSTRACT FROM AUTHOR]

Linear AC power supplies can be replaced by their nonlinear switching counterparts due to the lower voltage drops and higher efficiency and power density of switching-mode inverters. Multilevel cascaded H-bridge (CHB) converters are the preferred inverter structure because of modular configuration, control, and protection. The output voltage quality in CHB converters depends on the number of output levels. Asymmetric CHBs (ACHBs) produce an output voltage with higher number of levels with respect to CHBs for the same number of cascaded modules. This results in the reduction of power supply size, voltage drops, and losses. Considering the relative high switch counts, analysis of the effect of conduction and dead-time voltage drops on the inverter output characteristics is an important challenge in designing multilevel converters. In this paper, a generic algorithm is presented to calculate the conduction and dead-time voltage drops of ACHBs utilizing level-shifted modulation. These voltage drops give the necessary information for the design of heatsinks, switch selection, output impedance estimation, and the compensation schemes. It is shown through theoretical and simulation studies that the aforementioned voltage drops of ACHBs are to be calculated in a different manner with respect to the CHBs which mostly use the phase-shifted modulation. [ABSTRACT FROM AUTHOR]

The performance of Voltage Source Inverter (VSI) is affected by power semiconductor nonlinearities, dead time, and control delay. The compensation of these nonlinear effects is necessary to meet requirements in terms of current quality and high efficiency, especially for grid-connected power conversion systems. In this paper, the effects of nonlinearities are widely analyzed and a new compensation technique for a steady-state current-controlled VSI is proposed. It is based on a step-by-step voltage compensation on the basis of the current error evaluated within each control interval. As a result, a complete compensation is achieved within a whole period of the fundamental. To cope with the zero-current clamping effect, the proposed compensation technique is implemented in a recursive way. For slow-dynamic applications, such as photovoltaic systems, this method allows achieving high performance with very low computational requirements. [ABSTRACT FROM PUBLISHER]

A new dead time compensation method for a pulsewidth modulation (PWM) inverter is proposed. In the PWM inverter, voltage distortion due to the dead time effects produces fifth and seventh harmonics in the phase currents of the stationary reference frame, and a sixth harmonic in the d- and q-axis currents of the synchronous reference frame, respectively. In this paper, the sixth harmonic of the integrator output of the synchronous d-axis proportional-integral (PI) current regulator is used to compensate the output voltage distortion due to the dead time effects, since the integrator output has ripple corresponding to six times the stator fundamental frequency. The proposed method can be easily implemented by feedforwardly adding compensation voltages to the output reference voltage of the synchronous PI current regulator. The proposed method, therefore, has some significant advantages such as simple implementation without additional hardware, easy mathematical computation, no offline experimental measurements, and application in both the steady state and the transient state. The validity of the proposed compensation algorithm is shown through several experiments. [ABSTRACT FROM AUTHOR]

This paper addresses modeling and analysis of the dead-time effects in parallel pulsewidth-modulated (PWM) twolevel three-phase inverters. The main objective is to gain understanding of how the effects caused by the necessary blanking time, the finite turn-on and turn-off times of the switching devices, and the forward voltage drops of the switching devices and the antiparallel diodes, i.e., the dead-time effects, influence the circulating current generation between the parallel-connected units. To meet this objective, a circulating current model taking these effects into account is developed for the parallel connection of n units. The model, which is an average model by nature, can be used to study the circulating current behavior with different types of PWM methods and to estimate the resulting circulating current values when there are differences in the dead-time effect parameters. In other words, the model provides an analytical way to consider the significance of these effects. To verify the validity of the developed model, the circuit simulation and experimental results are shown and compared with the analytical results. The illustrations show that the results obtained with the developed model are in good agreement with the circuit simulations and the experiments. [ABSTRACT FROM AUTHOR]

A novel dead-time elimination method is presented in this paper for voltage source inverters. This method is based on decomposing of a generic phase-leg into two basic switching cells, which are configured with a controllable switch in series with an uncontrollable diode. Therefore, dead-time is not needed. In comparison to using expensive current sensors, this method precisely determines the load current direction by detecting which anti-parallel diode conducts in a phaseleg. A low-cost diode-conduction detector is developed to measure the operating state of the anti-parallel diode. In comparison with complicated compensators, this method features simple logic and flexible implementation. This method significantly reduces the output distortion and regains the output RMS value. The principle of the proposed dead-time elimination method is described in detail. Simulation and ex- perimental results are given to demonstrate the validity and features of this new method. [ABSTRACT FROM AUTHOR]

A new dead-time compensation method for vector-controlled ac motor drives is proposed. The method only compensates the fundamental and sixth harmonic component of the inverter-output distortions in synchronous reference frame. The fundamental component is compensated by feedforwardly adding a predetermined compensation signal to the voltage reference of ac motor drive. To compensate the harmonic distortions, the harmonic compensator with all-pass-based adaptive bandpass filter is proposed and builds up the feedback loop with current controllers in order to minimize the distortions due to dead-time effects. The method is software intensive and independent of the polarity of the phase currents and nonlinear-switching characteristics varied with operating conditions of the inverter. It is simulated and implemented on a 750-W laboratory ac motor drive, where its effectiveness is verified. [ABSTRACT FROM AUTHOR]

This paper presents an adaptive dead-time compensation strategy to obtain fundamental phase voltage for inverter fed vector controlled permanent magnet synchronous motor drives. The amplitude of phase dead-time compensation voltage (DTCV) to compensate disturbance voltage due to undesirable characteristics of inverter, such as dead-time, turn-on/off time of switching devices, and on-voltages of switching devices and diodes is adaptively determined according to a dead-lime compensation lime (DTCT). DTCT is identified on-line with using a δ-axis disturbance voltage in the current reference frame that is synchronized with current vector. The δ-axis disturbance voltage is estimated by a disturbance observer. The accuracy of identified DTCT is experimentally confirmed by calculating the mean absolute percentage error (MAPE) between a calculated active power and a measured one. MAPE for adaptive DTCT is almost within 5% at any operating point. [ABSTRACT FROM AUTHOR]

Presents information on a study which analyzed the dead-time effect and compensations of three-level neutral point clamp inverters for high-performance drive applications. Dead-time effect of three-level neutral point clamp inverter; Software compensation techniques and experimental comparisons; Conclusions.

Aimed at the problem that the auxiliary commutation circuit (ACC) of auxiliary resonant commutated pole (ARCP) inverters has a high loss in commutation processes, this paper presents a novel modulation strategy with shunt dead time based on a double ARCP (DARCP) inverter. In comparison with the original modulation strategy, this modulation strategy cannot only achieve soft switching for all switches, but also avoid the superposition of resonance current and load current at commutation moments in double ACCs (DACCs) and make the maximum current through DACCs approximately equal to load current in commutation processes. So, the circulating current loss in DACCs and the current stress of auxiliary switches can be effectively reduced. According to the equivalent circuits in different operation modes under the novel modulation strategy, this paper analyzes the operation principle, soft-switching implementation condition, and optimal parameter design procedure of the DARCP inverter. Finally, a 10-kW–16-kHz DARCP inverter prototype with insulated gate bipolar transistor-based switches is built. Experimental results are given to demonstrate the validity and features of the DARCP inverter under the novel modulation strategy. [ABSTRACT FROM AUTHOR]

This paper proposes a technique to compensate the effects of dead time in sinusoidal pulsewidth-modulated voltage-source inverters. The compensation is implemented by adjusting the switching frequency to avoid unfeasible pulsewidths of the gating signals, as well as to minimize the total harmonic distortion of the inverter output voltage. The technique can be used at any switching frequency, but the best results are obtained in the high-frequency range. The experimental results of the proposed technique that is applied in a three-phase induction motor drive system are presented. [ABSTRACT FROM AUTHOR]

A novel high-efficiency space vector modulation (SVM) strategy is proposed in this paper. It is based on the simultaneous and combined use of two strategies. The former consists of commutating only one switch of each inverter leg within each modulation period. In this way, there is no need to impose the dead time. The latter performs a step-by-step change of the modulation frequency in order to reduce the distortion of the inverter output voltage. The proposed system has been implemented and carried out on a programmable logic device (PLD) digital board. For validation, an experiment has been set up and several tests have been performed. The results have been compared with the ones achieved by means of the traditional SVM technique. [ABSTRACT FROM AUTHOR]

Presents a predictive algorithm which allows the compensation of the dead-time effects in a voltage-source inverter feeding an induction motor with space-vector pulsewidth modulation. Effects of dead time in a voltage-source pulsewidth modulation inverter; Simulation analysis to test the validity of the algorithm; Results and discussion.

Numerous studies have been carried out to compensate or eliminate the dead-time effect. This paper analyzes the limitations of the previous compensation or elimination schemes. Then, a novel mixed pulsewidth-modulation scheme for dead-time elimination and compensation is proposed for the grid-tied inverter. The proposed scheme implements the dead-time elimination in most of the grid current fundamental period but switches to the conventional dead-time compensation around the zero-crossing point. In this way, a safe and efficient dead-time effect elimination method is achieved. Furthermore, this paper proposes to determine the switching point and the compensation direction by the grid current modulation function. Experimental results are given to demonstrate the validity and features of the proposed method. [ABSTRACT FROM AUTHOR]

Dead-time and switch voltage drops represent the most important sources of distortion of the (average) output voltage in pulsewidth modulation inverters. Their effect is a function of the parameters of the drive system and of the operating conditions and is often intolerable in many drives applications, thus requiring a proper compensation strategy. Many techniques are implemented in industrial drives and reported in the literature, even very recently. Differently from standard approaches, the proposed methodology is based on a detailed physical model of the power converter (including output capacitance), described by a small set of parameters. A novel self-commissioning identification procedure is introduced, adopting multiple linear regression. The technique is tested on a commercial drive in comparison with state-of-the-art techniques. In addition, back electromotive force estimation improvements in a permanent-magnet synchronous motor sensorless drive system are shown to provide additional validation of the method. [ABSTRACT FROM PUBLISHER]

This study presents a new software-based plug-in dead-time compensator for grid-connected pulsewidth modulated voltage-source inverters of single-stage photovoltaic (PV) systems using predictive current controllers (PCCs) to regulate phase currents. First, a nonlinear dead-time disturbance model is reviewed, which is then used for the generation of a feed-forward compensation signal that eliminates the current distortion associated with current clamping effects around zero-current crossing points. A novel closed-loop adaptive adjustment scheme is proposed for fine tuning in real time the compensation model parameters, thereby ensuring accurate results even under the highly varying operating conditions typically found in PV systems due to insolation, temperature, and shadowing effects, among others. The algorithm implementation is straightforward and computationally efficient, and can be easily attached to an existent PCC to enhance its dead-time rejection capability without modifying its internal structure. Experimental results with a 5-kW PV system prototype are presented. [ABSTRACT FROM AUTHOR]

To prevent short-circuits between the upper and lower switches of power converters from over-current protection, the dead time is mandatory in the switching gating signal for voltage source converters. However, this results in many negative effects on system operations, such as output voltage and current distortions (e.g., increased level of fifth and seventh harmonics), zero-current-clamping phenomenon, and output fundamental-frequency voltage reduction. Many solutions have been presented to cope with this problem. First, the dead-time effect is analyzed by taking into account factors such as the zero-clamping phenomenon, voltage drops on diodes and transistors, and the parameters of inverter loads, as well as the parasitic nature of semiconductor switches. Second, the state-of-the-art dead-time compensation algorithms are presented in this paper. Third, the advantages and disadvantages of existing algorithms are discussed, together with the future trends of dead-time compensation algorithms. This article provides a complete scenario of dead-time compensation with control strategies for voltage source converters for researchers to identify suitable solutions based on demand and application. [ABSTRACT FROM AUTHOR]

Presents an approach to accurately compensate the dead-time effect in sinusoidal pulsewidth modulation (PWM) voltage-fed inverters. Key waveforms of the PWM inverter; States of power transistors, diodes and phase voltage; System block diagram for PWM inverters with time delay circuit.

This study proposes a technique to mitigate common-mode voltages with dead time effects taken into account in three-phase voltage source inverters (VSIs), on the basis of finite-set model predictive control methods. The effects of dead time on common-mode voltage in three-phase VSIs controlled by the model predictive control method are investigated. On the basis of the investigation, a common-mode voltage reduction method is proposed, which is not affected by the inevitable dead time of the VSIs. The proposed method pre-excludes, from the candidates for future vectors, those voltage vectors which can increase the common-mode voltage during the dead time. In addition, when zero vectors are chosen as an optimal vector from the standpoints of current errors, each zero vector is replaced with two non-zero vectors in opposite directions, so as not to deteriorate current performance by simply excluding the zero vectors. On the basis of the proposed pre-selective technique, the proposed method can restrict the common-mode voltage within ±Vdc/6 of the three-phase VSIs, whereas the common-mode voltages of the conventional method vary within ±Vdc/2. Simulation and experimental results are presented to verify the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Presents an analytical technique for calculating the harmonic characteristics of the output voltage of an H-bridge inverter with dead time. Description of the three-dimensional model for generating the pulsewidth-modulated (PWM) pulse train; Harmonic characteristics of an H-bridge PWM inverter with dead time; Discussion of the simulation results.

The selective harmonic control (SHC) method of pulsewidth modulation is meant to place switching edges to eliminate or set precisely given harmonics. This manuscript discusses the practical impact of edge placement sensitivity due to dead time that occurs in generalized SHC. It further provides experimental validation to theoretical work presented in a previous publication. [ABSTRACT FROM AUTHOR]

A voltage-source inverter without dc-link components is an ac-to-ac converter having dual bridges of a pulsewidth-modulated (PWM) rectifier and a PWM inverter that can be controlled independently. While conventional matrix converters have disadvantages, such as a complicated commutation scheme and necessity of a large-sized clamp circuit, commutation, and protection of our inverter can be implemented easily. In order to control the PWM rectifier and the PWM inverter independently, snubber circuits for the PWM rectifier are required to assure the path of load current during dead time. In this paper, analytical method of a snubber circuit and operating characteristics of a snubber circuit are described when a O.75-kW induction motor is driven by our inverter. [ABSTRACT FROM AUTHOR]

Presents information on a study which focused on a on-line dead-time compensation technique for low-cost open-loop pulsewidth modulation voltage-source inverter drives. Volt-second compensation; Experimental results; Conclusions.

A generalised n-level multilevel converter that has no shoot-through problem and thus is operated without dead time at each commutation is proposed. It is obtained by modifying the traditional neutral-point clamped multilevel converter topology based on dual-buck converter concept. The m-phase n-level converter can be readily constructed by using the proposed multilevel converter topology. The half-bridge five-level inverter, as an example case, is presented along with the operating principle and modulation and control methods. Experimental results show the feasibility and validity of the proposed converter. [ABSTRACT FROM AUTHOR]

A simple and iterative algorithm is devised in this letter with the help of the small-gain theorem to determine the current polarities of pulsewidth-modulation voltage-source-inverter drives. Experimental results are also presented to show the effectiveness of the method when used in the dead-time compensation. [ABSTRACT FROM AUTHOR]

This paper proposes a novel three-phase voltage source inverter dead-time compensation strategy for accurate compensation in wide current regions of the inverter. In particular, an analysis of the output voltage distortion of the inverter, which appears as parasitic components of the switches, was conducted for proper voltage compensation in the low current region, and an on-line compensation voltage controller was proposed. Additionally, a new trapezoidal compensation voltage implementation method using the current phase was proposed to simplify realizing the trapezoidal shape of the three-phase compensation voltages. Finally, when the proposed dead-time compensation strategy was applied, the maximum phase voltage magnitude in the linear modulation voltage regions was defined to achieve smooth operation even at high modulation index. Simulations and experiments were conducted to verify the performance of the proposed dead-time compensation scheme. [ABSTRACT FROM AUTHOR]

Grid background and dead‐time harmonic perturbations pose challenges in maintaining power quality and stability in the grid integration of renewable energy conversion systems. Therefore, a super‐twisting algorithm with the ability to reject harmonic perturbations on three‐phase grid‐tied inverters is proposed. The algorithm design is related to dead‐time and grid background harmonics so that robust performance is achieved under these perturbations. To highlight the advantages of the proposed algorithm, it is compared against proportional‐integral (PI) control in several dead‐time and grid background harmonic sweeps. The maximum inverter current distortion obtained with PI control in simulation is 15.53%. However, by using the proposed algorithm instead, the maximum current distortion is reduced to 1.8%. Dead‐time is experimentally swept by using a permanent magnet motor as a harmonic‐free grid. Experimental results of grid background harmonics are obtained by injecting reactive energy into a grid with 2.19% voltage distortion. When PI control is used in the experimental setup, the maximum inverter current distortion obtained is 11.4%. However, with the proposed algorithm, the maximum current distortion is reduced to 1.5%, which complies with the standard IEEE 1547‐2018. [ABSTRACT FROM AUTHOR]

The extra-LC auxiliary-resonant-snubber-based converter (ELCARSC), as a soft-switching converter, has the advantages of low switching loss, low electromagnetic interference noise, and low-output distortion caused by the dead-time effect. However, the dead-time effect is still the main problem in a high-precision application. Besides, the traditional control and compensation methods rely on the accuracy of the circuit parameters, especially the junction capacitance, thus resulting in compensation error. Therefore, this paper proposed a novel high-precision control method through modulating the initial resonant current to eliminate the dead-time effect of ELCARSC. The method does not need complicated online calculation and reduces the dependence on the accuracy of the circuit parameters, especially the influence of the junction capacitances of the switches. In this paper, the dead-time effect of the ELCARSC is analyzed. The output voltage error with the conventional variable-timing control method is analyzed. Subsequently, the proposed modulated initial resonant current control is introduced. Finally, a prototype was developed that verified the effectiveness of the control method. The quality of the output current and voltage is improved by utilizing the proposed control method. However, the peak current of the auxiliary switch is increased. [ABSTRACT FROM AUTHOR]

In this paper, a new zero-sequence current suppression control strategy for the five-phase open-winding fault-tolerant fractional-slot concentrated-winding interior-permanent-magnet (FTFSCW-IPM) motor drive system with a common dc bus is proposed. By unequal distribution of the zero voltage vector, the proposed method can well suppress the zero-sequence current caused by the dead-time effect that the conventional eliminating method cannot be achieved. First, the dead-time effect to the zero-sequence current is discussed. Then the zero-axis controller is designed to obtain the reference common-mode voltage. Last, according to the principle of the unequal zero voltage vector distribution, the switching sequence of the two inverters can be calculated, and the maximum modulation index is also first deduced in detail. The proposed method is proved by the simulation and experimental results. [ABSTRACT FROM AUTHOR]

Model predictive control (MPC) strategies have been frequently studied in recent years. To reduce the common-mode voltage (CMV) as well as the current total harmonic distortions (THDs) of the 2-level voltage sources (2L-VSIs), a new MPC strategy is proposed in this study considering both the dead-time and the one-step delay effects. First, the reference voltage vector (VV) prediction based MPC strategy is utilised as it is simple and accurate. Next, the VV preselection strategy is studied in detail to remove the CMV spikes. The effects of the dead time on the CMV are analysed, and an improved VV preselection strategy is presented to reduce the CMV spikes. Then, the one-step delay effects are also analysed, and further improvements are made to completely remove the CMV spikes. Moreover, the maximum variation of the current during one control period is studied in-depth to provide a solid theory foundation for dividing the current sector more accurately. As the six non-zero VVs of the 2L-VSI are fully used in the proposed method, not only the CMV but also the current THDs are reduced. Finally, comparative simulation and experimental studies are carried out to validate the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

This paper analyzes the use of the voltage distortions in pulse width modulation voltage-source inverters caused by the inverter switching for islanding detection purposes. The nonideal characteristics of the inverters, mainly due to the dead time needed to have safe commutations, produce fundamental frequency-dependent harmonics (−5th, 7th, …) in the output voltage. These harmonic order are, in principle, an unwanted effect, as they reduce the power quality. However, they can potentially be used for islanding detection purposes. The physical principles of the method would be the same as for high-frequency signal injection methods that have already been proposed, but without the need of injecting a high-frequency signal, behaving, therefore, as a passive islanding detection technique. [ABSTRACT FROM AUTHOR]

Cascaded H-bridge (CHB) multilevel inverters (MLIs) have been widely used for power electronics systems. While high-voltage blocking across power switches is not a constraint for low voltage applications, the research trend has been oriented to the design of more compact module topologies as an alternative for CHB. Despite the generation of more voltage levels with reduced switch count, the existing module topologies in recent literature take no account of the freewheeling current path during dead-time, thus, inducing multistep jumps in voltage levels and giving rise to undesirable voltage spikes. Addressing this concern, this paper proposes two symmetrical compact-module topologies for cascaded MLI, where freewheeling current path during dead-time is provided for smooth transition between voltage levels to prevent voltage spikes. The proposed 7-level and 13-level compact-modules demonstrated low number of conducting switches for all voltage levels. Comprehensive analysis and comparison with the latest module topologies are conducted. To validate the operation of the proposed compact-module topologies, simulation and experimental results are presented. [ABSTRACT FROM PUBLISHER]

The injected grid current of the voltage-controlled grid-connected inverter has serious distortion due to the low frequency harmonic components in the output voltage, which is resulted by the dead time of the drive signals of the power switches, and the distortion cannot be eliminated even when an output voltage closed loop is incorporated. This paper introduces a virtual series impedance to increase the output impedance of the grid-connected inverter only at the dominated lower harmonic frequencies; thus, the injected grid current quality can be improved and the dynamic performance of the grid-connected inverter is not deteriorated. Experimental results from a 6-kW single-phase grid-connected inverter confirm the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]