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An electrostatic discharge (ESD)-protected one-time-programmable (OTP) memory front-end circuit, for high-voltage (HV) applications, designed and manufactured in silicon-on-insulator (SOI) technology, is presented. The SOI technology meets HV functional-isolation and level-shifting requirements but is not suitable for advanced analog circuits. The presented OTP memory is discussed as an introduction to digital programmability in the considered technology. The memory element consists of an antifuse type structure and is implemented using a 5-V nMOS with $\text {L}={1}\,\, \mathbf {\mu \text {m}}$ and $\text {W}={1.2}\,\, \mathbf {\mu \text {m}}$ . The cell memory allows for significant area and power savings in the adopted HV technology. Conditions for this require that an efficient ESD protection will guarantee safe operation, even in the presence of a small and fragile on-chip element whose undesired burning would compromise the programming mechanism, and consequently the reliability, of the circuit. Details about the circuit design implementation of the front-end circuit for both read and write circuits and ESD protection are described with experimental results validating the proposed implementation.

This paper presents the design and experimental characterization of a Proton Sound Detector (ProSD), a device that physically captures and senses the weak acoustic signal emitted by the fast energy deposition at the end of the same proton beam range. The measured acoustic signal Time-of-Flight provides a very accurate ( $13~\mu \text{m}$ accuracy) measure of the proton beam penetration depth in water, improving the proton range verification accuracy w.r.t. previous works in pre-clinical scenarios. This suggests interesting possibilities for high-accuracy and real-time beam monitoring and calibration in hadron-therapy for cancer treatment. The detector has been fully characterized and tested with a physical 20 MeV proton beam in a water energy absorber. The ProSD and the water tank have been mounted in front of the exit layer of a 20 MeV 120 ns pulse time-width proton beam. A clear sinusoidal-like acoustic signal of 5 Pa and 2.3 MHz frequency has been detected at 12 dB SNR with 0.8 Gy single shot dose. After averaging 10 beam shots the achieved Signal-to-Noise-Ratio is 22 dB allowing a $\pm 7.5~\mu \text{m}$ precision vs. previously reported $\pm 45~\mu \text{m}$ ionoacoustic precision.

The dental environment can be considered a stressor for children, and can trigger unwanted behaviors. Pediatric Dentistry is a specialty that requires professionals to know preventive measures and restorative skills to perform dental treatment in children or adolescents. In addition, it is especially important that the professional is concerned with the child’s feelings and reactions, allowing the pediatric dentist to identify situations that may generate stress for the patient during the care, and manage the presented behaviors. Recent studies have measured children’s reactions and feelings during dental treatments using projective techniques. Given the importance of drawing to identify children’s emotions, the objective of this study was to search the literature about the use of drawings as a projective technique in Pediatric Dentistry. Therefore, projective techniques, with an emphasis on drawing, have proved to be an effective instrument to be used in clinical practice to better understand the reactions presented by children during dental care and their relationship with dentists. Thus, avoiding unexpected situations in the office and allowing greater chances of obtaining a positive return from the patient.

This paper presents a 4th-order low-pass continuous-time Diode-RC filter with 24 MHz cut-off frequency. The filter structure is based on the combination of positive (passive) and negative (using cross-coupled MOS transistors) cells to synthesize complex-conjugate-poles pairs. Moreover, the filter is designed and optimized to have high-linearity along all the filter pass-band. The filter exhibits 16 dBm-$$\text {IIP}_3$$ with 2–3 MHz input tones and 5 dBm-$$\text {IIP}_3$$ with 23–24 MHz, whereas the current consumption remains limited to $$100 \, \upmu \hbox {A}$$ from 1.8 V supply voltage.

This paper characterizes and models the effects of total ionizing dose (TID) up to 1 Grad(SiO2) on the drain leakage current of ${n}$ MOSFETs fabricated with a commercial 28-nm bulk CMOS process. Experimental comparisons among individual ${n}$ MOSFETs of various sizes provide insight into the TID-induced lateral parasitic devices, which contribute the most to the significant increase up to four orders of magnitude in the drain leakage current. We introduce a semiempirical physics-based approach using only three parameters to model the parallel parasitic and total drain leakage current as a function of TID. Taking into account the gate independence of the drain leakage current at high TID levels, we model the lateral parasitic device as a gateless charge-controlled device by using the simplified charge-based Enz–Krummenaker–Vittoz (EKV) MOSFET model. This approach enables us to extract the equivalent density of trapped charges related to the shallow trench isolation oxides. The adopted simplified EKV MOSFET model indicates the weak inversion operation of the lateral parasitic devices.

Since 2015 slow-release oral morphine (SROM) is approved for opioid substitution treatment (OST) in Germany. The SROMOS study (efficacy and tolerability of slow-release oral morphine in opioid substitution treatment) evaluates the efficacy and safety of SROM in routine care. This article describes the switching process from racemic methadone, levomethadone and buprenorphine to SROM. Between July 2016 and November 2017 180 patients in 23 study centers in Germany were included in the prospective, non-interventional, naturalistic observational study. Patients were already in OST and switched from a previous medication to SROM. The switching process was analyzed during a period of fourteen days. Data were available for 169 participants. The switching process had a different progression depending on premedication and pre dosage. On the fourteenth day of SROM treatment patients switched from racemic methadone took an average dosage of 922.2 mg/day, from levomethadone 801.0 mg/day and from buprenorphine 626.7 mg/day. Average conversion ratio racemic methadone to SROM was 1:11.8, levomethadone to SROM 1:17.4 and buprenorphine to SROM 1:58.0. This study provides the first data on the switching process from buprenorphine to SROM. Average dose ratio racemic methadone to SROM on the fourteenth day of treatment was considerably higher than recommended in the prescribing information.

This paper presents a fourth-order continuous-time analog filter based on the cascade of two flipped-source-follower (FSF) biquadratic (biquad) cells. The FSF biquad adopts two interacting loops (the first due to the classic source-follower, and the second to the additional gain path) which lower the impedances of all circuit nodes with relevant benefits in terms of noise power reduction and linearity enhancement. The presented device was integrated in 28 nm CMOS and featured 100 MHz −3 dB bandwidth with 67 dB Dynamic-Range. Input IP3 was 12 dBm at 10 and 11 MHz input tone frequencies. Total power consumption was 0.968 mW (0.484 mW per cell). Hence, the filter performed one of the highest figures-of-merit (160.7 dBJ-1) compared with analog state-of-the-art filters.

Reverse bandgaps generate PVT-independent reference voltages by means of the sums of pairs of currents over individual matched resistors: one (CTAT) current is proportional to VEB, the other one (PTAT) is proportional to VT (Thermal voltage). Design guidelines and techniques for a CMOS low-power reverse bandgap reference are presented and discussed in this paper. The paper explains firstly how to design the components of the bandgap branches to minimize circuit current. Secondly, error amplifier topologies are studied in order to reveal the best one, depending on the operation conditions. Finally, a low-voltage bandgap in 65 nm CMOS with 5 ppm/°C, with a DC PSR of −91 dB, with power consumption of 5.2 μW and with an area of 0.0352 mm2 developed with these techniques is presented.

OTP (One Time Programmable) memory in power technology enables electrical performance optimization together with area occupation reduction. In this paper, the aspects relative to the oxide breakdown (which is the key mechanism for memory programmability) are studied and applied to the development of an antifuse OTP cell in a 350 nm-CMOS power technology. The physical analysis of the degradation phases of an oxide layer is presented together with the physical models, exploited to foresee the device time-to-breakdown depending on applied voltage, oxide thickness etc. The achieved results are used in the development and reliable implementation of OTP cells in the target 350 nm-CMOS node.

This work describes the development methodology of an electronic device. All the phases, starting from the definition of the specifications up to the fabrication of the device, will be explained using the evolution of a project aimed at developing a high-performance DC-DC converter for LED driver application as a use case. The project involves teams and experts from the technology department, the product development and the fabrication. It is therefore important to have an efficient process flow, ensuring the optimal communications and information transmission between the teams. In addition, the project here presented introduces a novelty regarding the concept phase. The use of a rapid control prototyping tool, called dSPACE, guarantees the feasibility of a concept circuit before proceeding directly with the design phase, avoiding time-wasting. In fact, the mentioned emulator allows the preliminary evaluation of the circuit in ideal conditions and, subsequently, a more real study on hardware.

This study presents a novel low-pass continuous-time filter based on the voltage flipped-source-follower (SF). The filter efficiently operates in CMOS 28 nm and improves the SF filters state-of-the-art thanks to a dedicated circuit that operates in fully-differential fashion (instead of the pseudo-differential typically used in state-of-the-art SF filters) with a dedicated Common-Mode-Feedback circuit. Thus this work extends the application of the SF filtering stages to the nm-range technologies where threshold voltage ( V TH ) is only two times lower than the supply voltage ( V DD ) for what regards standard-process MOS transistors. In order to validate the design concept, the proposed filter has been designed in CMOS 28 nm technology. Extensive simulation results of a 131 MHz -3 dB frequency proof-of-concept second-order filter are proposed. The device consumes 510 μW power from a single 1 V supply-voltage. In-band integrated noise is 160 μV RMS and IIP3 is 19 dBm for 20 and 21 MHz input tones frequencies. Simulation results lead to 166 J -1 figure-of-merit, outperforming the analogue filter state-of-the-art.

This paper presents the design and experimental characterization of a 28 nm Complementary Metal Oxide Semiconductor (CMOS) Analog Front-End (AFE) for fast-tracking small-diameter Muon Drift-Tube (sMDT) detectors. The device exploits an innovative analog signal processing that allows a strong increase in the detection rate of events and significantly reduces the impact of fake/pile-up events, which often corrupt incident radiation energy events. The proposed device converts the input charge coming from incident radiations into voltage by a dedicated Charge-Sensitive Preamplifier (CSPreamp). Therefore, the fast-tracking concept relies on sampling the slope of the CSPreamp output voltage and using it for detecting both the incident event arrival instant and the amount of charge that has been effectively read out by MDT detectors. This avoids the long processing times intrinsically needed for baseline recovery transient, during which the detected signal can be severely corrupted by additional and unwanted extra-events, resulting in extra-charge (and thus in CSP output voltage extra-transient) during the signal roll-off. The proposed analog channel operates with a 5&ndash, 100 fC input charge range and has a maximum dead-time of 200 ns (against the 545 ns of the state-of-the-art). It occupies 0.03 mm2 and consumes 1.9 mW from 1 V of supply voltage.

OBJECTIVE The objective of this study was to assess caesarean section (CS) rates before and after the implementation of the Project Appropriate Birth (PPA), based on the Robson ten group classification system. DESIGN A before-and-after study. SETTING Maternity hospital in South Brazil. POPULATION All pregnant women attending from April 2016 to April 2017 (period 1, pre-implementation of PPA) and from June 2017 to June 2018 (period 2, post-implementation of PPA). METHODS Maternal and obstetric characteristics were evaluated, including Robson's classification, based on the characteristics of pregnancy and childbirth. A chi-square test and crude and adjusted relative rates were used to analyse the study variables. The significance level was set at 5%. MAIN OUTCOME MEASURES The CS rate for each group, their contribution to the overall CS rate and the differences in these contributions before and after PPA implementation. RESULTS The CS rates decreased from 62.4 to 55.6%, which represented a 10.9% reduction after the implementation of the PPA. Pregnant women in Robson classification groups 1-4 had a 21.4% reduction in CS rates, ranging from 49.1 to 38.6%. The greatest contributors to the overall CS rates were group 5 and group 2, accounting for more than 60% of the CS deliveries. CONCLUSION The study results suggest that Project Appropriate Birth had an impact on the reduction of CS rates, especially in Robson classification groups 1 through 4, which indicates that providing mothers with evidence-based interventions for labour and childbirth assistance contributed to reduce CS rates. TWEETABLE ABSTRACT The Project Appropriate Birth is an innovative project that has demonstrated promising results, suggesting that interventions based on scientific evidence can lead to real changes in childbirth care, contributing to reduce CS rates. The aim of the PPA is to promote activities to improve childbirth care and encourage vaginal delivery. In this study, 6238 pregnant women admitted to the hospital for delivery were included and classified into one of the Robson 10-group classification. Findings revealed a 10.9% reduction in the overall CS rate and a 21.4% reduction for pregnant women in Robson classification groups 1 through 4, after the implementation of the PPA.

Real-time neural spike detection is an important step in understanding neurological activities and developing brain-silicon interfaces. Recent approaches exploit minimally invasive sensing techniques based on implanted complementary metal-oxide semiconductors (CMOS) multi transistors arrays (MTAs) that limit the damage of the neural tissue and provide high spatial resolution. Unfortunately, MTAs result in low signal-to-noise ratios due to the weak capacitive coupling between the nearby neurons and the sensor and the high noise power coming from the analog front-end. In this paper we investigate the performance achievable by using spike detection algorithms for MTAs, based on some variants of the smoothed non-linear energy operator (SNEO). We show that detection performance benefits from the correlation of the signals detected by the MTA pixels, but degrades when a high firing rate of neurons occurs. We present and compare different approaches and noise estimation techniques for the SNEO, aimed at increasing the detection accuracy at low SNR and making it less dependent on neurons firing rates. The algorithms are tested by using synthetic neural signals obtained with a modified version of NEUROCUBE generator. The proposed approaches outperform the SNEO, showing a more than 20% increase on averaged sensitivity at 0 dB and reduced dependence on the neuronal firing rate.

OBJECTIVE: The objective of this study was to evaluate C-section rates, before and after the implementation of the Project Appropriate Birth based on the Robson 10-group classification system. DESIGN: An observational, cross-sectional study. SETTING: Maternity hospital in South Brazil. POPULATION: All pregnant women attending, April 2016 through April 2017 (phase 1, pre-implementation of the Project Appropriate Birth) and June 2017 through June 2018 (phase 2, post-implementation of the Project Appropriate Birth). METHODS: Maternal and obstetric characteristics were evaluated, including Robson’s classification, based on the characteristics of pregnancy and childbirth. Chi-square test and crude and adjusted prevalence ratios were used to analyze study variables. The significance level was set at 5%. MAIN OUTCOME MEASURES: C-section rate for each group, their contribution to the overall c-section rate and the differences in these contributions before and after PPA implementation. RESULTS: C-section rates decreased from 62.4% to 55.6%, which represented a 10.9% reduction after the implementation of the Project Appropriate Birth. Pregnant women in Robson classification groups 1 through 4 had the greatest decrease in C-section rates, ranging from 49.1% to 38.6%, which represents a 21.5% reduction. The greatest contributors to the overall C-section rates were group 5 and group 2, accounting for more than 60% of the C-section deliveries. CONCLUSION: The Project Appropriate Birth had an important impact on the reduction of C-section rates, especially in Robson classification groups 1 through 4, which indicates that providing mothers with evidence-based interventions for labor and childbirth assistance will contribute to reduce C-section rates.

This randomized parallel-group control trial tested the efficacy of distraction using audiovisual eyeglasses (AVE) during dental procedures [NCT03902158]. Forty-four 6–9 year-old children with low/moderate anxiety and who needed restorative treatment or exodontia of the primary molars were randomly allocated into two groups: the AVE (experimental) and the conventional behavior management techniques (control) groups. Motion sensors were used to measure the participants’ body movements. Dental visits were video recorded, and their pain levels and behavior were assessed using the Faces, Legs, Activity, Cry, and Consolability Behavioral Pain Assessment Scale and the Venham Behavioral Scale, respectively. Anxiety was assessed via heart rate measurements. After treatment, the children scored their pain using the Faces Pain Scale. Mann-Whitney U and chi-square tests were used to compare the groups. The mean score on the behavioral scale was 0.59 in the experimental group and 0.72 in the control group under local anesthesia (p = 0.73). During the procedure, the mean score was 0.41 in the experimental group and 1.32 in the control group (p = 0.07). The mean heart rate was similar in both groups (p = 0.47), but a significant increase during treatment was observed in the control group. There was no difference between the groups in terms of pain, behavior, and self-reported pain scores (p = 0.08). Children aged 6-7 who used the AVE had fewer wrist movements (435.6) than that of children in the control group (1170.4) (p = 0.04). The AVE achieved similar results to the basic behavior management techniques, with good acceptance by the children.

This paper presents a generalized EKV charge-based MOSFET model that includes the effects of trapped charges in the oxide bulk and at the silicon/oxide interface. It is shown that in the presence of oxide- and interface-trapped charges, the mobile charge density can still be linearized but with respect to both the surface potential and the channel voltage. This enables us to derive closed-form expressions for the mobile charge density and the drain current. These simple formulations demonstrate the effects of charge trapping on MOSFET characteristics and crucial device parameters. The proposed charge-based analytical model, including the effect of velocity saturation, is successfully validated through measurements performed on devices from a 28-nm bulk CMOS technology. Ultrahigh total ionizing doses up to 1 Grad(SiO2) are applied to generate oxide-trapped charges and activate passivated interface traps. Despite a small number of parameters, the model is capable of accurately capturing measurement results over a wide range of device operation from weak to strong inversion. Explicit expressions of device parameters also allow for the extraction of the oxide- and interface-trapped charge densities.

This work presents a comparison between different neural spike algorithms to find the optimum for in vivo implanted EOSFET (electrolyte&ndash, oxide-semiconductor field effect transistor) sensors. EOSFET arrays are planar sensors capable of sensing the electrical activity of nearby neuron populations in both in vitro cultures and in vivo experiments. They are characterized by a high cell-like resolution and low invasiveness compared to probes with passive electrodes, but exhibit a higher noise power that requires ad hoc spike detection algorithms to detect relevant biological activity. Algorithms for implanted devices require good detection accuracy performance and low power consumption due to the limited power budget of implanted devices. A figure of merit (FoM) based on accuracy and resource consumption is presented and used to compare different algorithms present in the literature, such as the smoothed nonlinear energy operator and correlation-based algorithms. A multi transistor array (MTA) sensor of 7 honeycomb pixels of a 30 &mu, m2 area is simulated, generating a signal with Neurocube. This signal is then used to validate the algorithms&rsquo, performances. The results allow us to numerically determine which is the most efficient algorithm in the case of power constraint in implantable devices and to characterize its performance in terms of accuracy and resource usage.

This brief presents a novel biquadratic cell (biquad) based on the flipped-source-follower (FSF) circuit. The main idea is to exploit the FSF circuit as a basic building block for a low-pass second-order filter, taking advantage of its well-known strengths, like low-output impedance, low-noise, large in-band linearity, and low power. Thanks to the very essential FSF circuit, the resulting biquad is a power-efficient broad bandwidth stage, with very low-noise performance. In order to validate the biquad design idea, extensive circuital simulation results will be presented. The filter design example synthesizes a third-order low-pass transfer function and consumes 2.3 mW from a single 1.8 $\text{V} {@} {V} _{\text{DD}} $ . Input noise spectral density is 7 nV/vHz. Linearity has been evaluated in terms of IIP3 (25 dBm) and THD (−40 dBc at 380 ${\text{mV}}_{\text {0-PEAK}} $ output voltage swing, resulting in 62-dB SNR). Hence, a very promising figure-of-merit (i.e., 165 $\text{J}^{{-1}}$ ) has been achieved.

This paper presents a low power read-out front-end for 3-axis MEMS capacitive accelerometer. The front-end includes the analog preamplifier (to sense the signal coming from the MEMS) and a Successive-Approximation 10b A/D Converter, for digitalization and off-chip digital-signal-processing. Power minimization is achieved by using a continuous-time sensing preamplifier (i.e. constant-charge capacitance-to-voltage conversion) and SAR-ADC with bridge capacitive reduction. Preamplifier programmable in-band gain allows to accommodate different MEMS sensitivities. A very high-impedance MOS transistor is used for MEMS biasing, thus providing very low frequency (

This paper presents a Fast-Tracker front-end (FTfe) for ATLAS small-diameter Muon Drift Tube (sMDT) detectors of the Phase-II Upgrade HL-LHC. This design addresses the higher rate capability required by sMDT and reduced the dead-time below the maximum drift time, further increasing the efficiency. The front-end ensures a fast baseline restoration with a reset interval of maximum 160 ns, so that the secondary spurious pulses are avoided and the successive muon signals can be detected soon and correctly. The device has been designed in 1V-28nm-CMOS technology; outstanding 4.7mV/fC sensitivity and 0.24fC ENC are achieved with a core area of 0.03 mm2.

In order to fully exploit the physics potential of the ATLAS experiment at the HL-LHC, the trigger rate of and maximum latency of the first-level trigger system will be increased to 1 MHz and 10 μ s , respectively. In addition, a new first-level muon track trigger with high momentum resolution based on the ATLAS precision Muon Drift-Tube (MDT) chambers will be employed which requires triggerless readout. The TDC ASICs of the current front-end electronics of the MDT chambers are incompatible with these requirements. The front-end boards, each with a TDC chip and three 8-channel amplifier–shaper–discriminator (ASD) chips have to be replaced. Therefore, a new octal ASD2 ASIC has been developed in modern 130 nm IBM/Global Foundries CMOS technology. The chip also contains a Wilkinson ADC to perform both time-over-threshold and signal charge measurement. The ASD design has been fully qualified for the serial production of 80000 chips for ATLAS. The performance in terms of signal rise time and channel uniformity significantly surpasses the one of the previous chip while keeping the power consumption constant. In addition to the characterization with test pulses, several chips have been mounted on the front-end boards and tested in a muon beam at the Gamma Irradiation Facility GIF++ at CERN up to high counting rates where the superior drift time and spatial resolution becomes evident.

In this paper, the total ionizing dose (TID) response of a commercial 28-nm high-k CMOS technology at ultrahigh doses is measured and discussed. The degradation of pMOSFETs depends not only on the channel width but also on the channel length. Short-channel pMOSFETs exhibit a higher TID tolerance compared to long ones. We attributed this effect to the presence of the halo implantations. For short-channel lengths, the drain halo can overlap the source one, increasing the average bulk doping along the channel. The higher bulk doping attenuates the radiation-induced degradation, improving the TID tolerance of short-channel transistors. The results are finally compared and discussed through technology computer-aided design simulations.

Proton range verification by ionoacoustic wave sensing is a technique under development for applications in adron therapy as an alternative to nuclear imaging. It provides an acoustic imaging of the proton energy deposition vs. depth using the acoustic wave Time of Flight (ToF). State-of-the-art (based on simulations and experimental results) points out that this detection technique achieves better spatial resolution (< 1 mm) of the proton range comparing with Positron-Emission-Tomography (PET) and prompt gamma ray techniques. This work presents a complete Geant4/k-Wave model that allows to understand several physical phenomena and to evaluate the key parameters that affect the acoustic field generated by the incident proton radiation.

Oncological hadron therapy utilizes a beam of charged particles to destroy the tumor cells, exploiting the particular deposition curve that allow minimum damage to the surrounding healty tissues compared to traditional radiotherapy. Sulak and Hayakawa’s works have shown the applicability of this technique in clinical scenarios, but the lack of dedicated electronics for this type of experiments affects the spatial resolution that can be obtained with this technique [1]. This work presents an integrated analog front-end dedicated to ionoacoustic experiments that allows to estimate the position of the Bragg Peak with an average deviation of 1% with respect to the real position.

We present the prototype of a time-to-digital (TDC) ASIC for the upgrade of the ATLAS Monitored Drift Tube (MDT) detector for high-luminosity LHC operation. This ASIC is based on a previously submitted demonstrator ASIC designed for timing performance evaluation, and includes all features necessary for the various operation modes, as well as the migration to the TSMC 130 nm CMOS technology. We present the TDC design with the emphasis on added features and performance optimization. Tests of the timing performance demonstrate that this ASIC meets the design specifications. The TDC has a bin size of about 780 ps, and a timing bin variations within 40 ps for all 24 channels with leading and trailing edge digitization, while the power consumption has been limited to 250 mW, corresponding to a consumption of about 5.2 mW per edge measurement., Comment: 9 pages, 7 figures

A 3rd-order 132MHz cut-off frequency low-pass filter in 28nm CMOS-bulk technology is presented. Challenges related to the design of analog circuits in 28nm CMOS-bulk process node have been faced and mitigated operating at both architecture and circuit design level. The filter is based on an improved Active-gm-RC structure, where both poles of a Miller-compensated Opamp have been used for synthesizing the 3rd order filter transfer function. The proposed circuit solution enables high linearity (IIP3=11.5dBm at 21&22MHz input tones) even if the supply voltage is limited to 0.9V. Moreover, the power consumption is kept as low as 340μν without that the Signal-To-Noise ratio (60dB) is penalized. The achieved Figure-of-Merit is 164dB resulting the highest with respect to the state-of-The-Art.

In this paper, a fourth-order continuous-time follow-the-leader-feedback (FLFB) low-pass (LP) filter is presented. The outstanding FLFB noise behavior is exploited to minimize power consumption. This is achieved by means of customized implementation solutions based on combination of Active- RC /Active- $g_{m}$ - RC cells. The 0.18- $\mu \text{m}$ CMOS prototype performs 22.5-MHz −3 dB LP frequency response. Large linearity and dynamic range were achieved resulting in 21.5-dBm in-band (iB) IIP3 and 87- $\mu \text{V}_{\mathrm {RMS}}$ input referred iB integrated noise. The SNR for a −40 dB HD3 is 63 dB. The overall power consumption is 12.6 mW (i.e., 7 mA from a 1.8-V supply). The efficiency of the proposed technique is demonstrated by the achieved figure-of-merit (150.8 dB $\cdot ~\text{J}^{-1})$ , which favourably compares to the state-of-the-art active- RC analog filters.

A 28 nm CMOS-bulk lowpass analogue filter architecture is hereby proposed. The filter is based on an improved Active-Gm -RC structure, where both poles of a Miller-compensated operational amplifier (OPAMP) have been used for synthesising a third-order filter. Several well-known issues related to the 28 nm process node have been hereby mitigated by proper circuit/design techniques, enabling large signal-to-noise ratio (SNR) and 13.5 dBm IIP3. The proposed circuital solution performs 59 dB-SNR at 340 µW power consumption from a single 0.9 V supply-voltage. This allows one of the higher figure-of-merit (156 dB) in sub-1 V analogue filters state of the art.

This paper presents a transistor-level design with extensive experimental validation of a Content Addressable Memory (CAM), based on an eXclusive OR (XOR) single-bit cell. This design exploits a dedicated architecture and a fully custom approach (both in the schematic and the layout phase), in order to achieve very low-power and high-speed performances. The proposed architecture does not require an internal clock or pre-charge phase, which usually increase the power request and slow down data searches. On the other hand, the dedicated solutions are exploited in order to minimize parasitic layout-induced capacitances in the single-bit cell, further reducing the power consumption. The prototype device, named CAM-28CB, is integrated in the deeply downscaled 28 nm Complementary Metal-Oxide-Semiconductor (CMOS) Bulk (28CB) technology. In this way, the high transistor transition frequency and the intrinsic lower parasitic capacitances allow the system speed to be improved. Furthermore, the high radiation hardness of this technology node (up to 1Grad TID), together with the CAM-28CB high-speed and low-power performances, makes this device suitable for High-Energy Physics experiments, such as ATLAS (A Toroidal LHC ApparatuS) at Large Hadron Collider (LHC). The prototype operates at a frequency of up to 100 MHz and consumes 46.86 &micro, W. The total area occupancy is 1702 &micro, m2 for 1.152 kb memory bit cells. The device operates with a single supply voltage of 1 V and achieves 0.41 fJ/bit/search Figure-of-Merit.

This paper investigates the effects of total ionizing dose up to 1 Grad on 28-nm bulk MOSFETs under different bias conditions during irradiation. The aim is to assess the potential use of this commercial bulk CMOS technology in the future high-luminosity Large Hadron Collider at CERN that will require highly improved radiation-tolerant tracking systems.

This paper presents a reconfigurable discrete-time audio Sigma-Delta modulator implemented in 0.18-µm CMOS technology. The 600, µm, ×, 400, µm core area SD modulator is based on a 2, +, 2 MASH architecture, and features several different operating modes in which noise-shaping order, number of output word bits, sampling rate, and bandwidth can be programmed ad hoc. By design, the power consumption is minimized for the selected operating mode. The achieved performance ranges from 99-dB DR with 4th-order noise shaping and full standard audio bandwidth, while consuming 0.97 mW down to 85-dB DR with second order noise shaping over reduced bandwidth for vocal control operation, while consuming 100, µW. The developed device can be used either to read-out different sources (microphones) or to operate in different modes within the same system (i.e. with the same microphone in different scenarios). The trade-off between performance and re-configurability is the key element of this work.

Spatial resolution and efficiency of the ATLAS muon Monitored Drift Tubes (MDT) depend on drift time resolution, noise levels, and accurate threshold setting. A new 130 nm readout device is developed and optimized for the required time resolution, to guarantee rise times below 10 ns with acceptable time slewing effects. Moreover, the large chain-amplification results in increased sensitivity to any disturbance, mainly from the supply. To avoid additional costs to clean up the setup from such disturbances, the readout chain adopts innovative techniques at system, circuit, and design levels. These are minimizing readout chain disturbance sensitivity. This paper describes the achieved performance by showing measurement results and presenting resolution studies taken in a high energy test beam at CERN.

The high luminosity and interaction rate expected from the planned High Luminosity-Large Hadron Collider (HL-LHC) upgrade require a replacement and improvement of the ATLAS Muon-Drift-Tube (MDT) read-out electronics. This paper presents a Phase Locked Loop (ePLL) intended to be used inside the improved Time-to-Digital Converter (TDC), which digitizes the arrival time and charge amplitude information. Starting from a 40 MHz input clock, the ePLL provides output clocks of 160 MHz and 320 MHz with a phase resolution of 11.25° and 22.5°, respectively. The prototype, integrated in 130 nm CMOS technology, has 0.02 $mm^2$ of area and 1.2V of supply voltage.

This paper presents a multidisciplinary experiment where a population of neurons, dissociated from rat hippocampi, has been cultivated over a CMOS-based micro-electrode array (MEA) and its electrical activity has been detected and mapped by an advanced spike-sorting algorithm implemented on FPGA. MEAs are characterized by low signal-to-noise ratios caused by both the contactless sensing of weak extracellular voltages and the high noise power coming from cells and analog electronics signal processing. This low SNR forces to utilize advanced noise rejection algorithms to separate relevant neural activity from noise, which are usually implemented via software/off-line. However, off-line detection of neural spikes cannot be obviously used for real-time electrical stimulation. In this scenario, this paper presents a proper FPGA-based system capable to detect in real-time neural spikes from background noise. The output signals of the proposed system provide real-time spatial and temporal information about the culture electrical activity and the noise power distribution with a minimum latency of 165 ns. The output bit-stream can be further utilized to detect synchronous activity within the neural network.

Over the last decade, MEMS microphones have become the leading solution for implementing the audio module in most portable devices. One of the main drivers for the success of the MEMS microphone has been the continuous improvement of the corresponding integrated interface circuit performance in terms of both dynamic range and power consumption, which enabled the introduction in mobile devices of additional functionalities, such as Hi-Fi audio recording or voice commands. As a result, MEMS microphone interface circuits evolved from just simple amplification stages to complex mixed-signal circuits, including A/D converters, with ever improving performance. This paper provides an overview of such evolution based on actual design examples, focusing, finally, on the latest cutting-edge solutions.

Using the Y-function method, this paper experimentally investigates the effects of total ionizing dose up to 1 Grad on the channel mobility of a commercial 28-nm bulk CMOS process.

Resumo Objetiva-se verificar a associação entre o uso regular de serviços odontológicos e a perda dentária por idosos vinculados a onze Unidades de Saúde da Família no sul do Brasil. Estudo transversal que avaliou 438 idosos. Um questionário padronizado foi utilizado e as variáveis clínicas de saúde bucal foram obtidas por um dentista treinado. O relato do uso regular dos serviços odontológicos, desfecho do estudo, foi obtido por meio de pergunta única. Foram realizadas análises descritivas e regressão de Poisson com o Stata 12.0. Analisando as variáveis de exposição e desfecho do estudo, na regressão não ajustada, houve associação positiva do relato do uso regular dos serviços de saúde bucal dos idosos com 9-11 anos de estudo (RP = 3,89; IC95%1,77-8,58) em comparação aos idosos com menos de 4 anos de estudo, com até 9 dentes (RP = 2,50;IC95%19,0-5,72) e 10 ou mais dentes (RP = 3,89;IC95%1,58-9,57) em comparação aos idosos sem dentes. Ao considerar a exposição principal, perda dentária, na análise ajustada, os indivíduos com 10 ou mais dentes (RP = 3,51;IC95%1,37-8,99) apresentavam maiores prevalências de relato de uso regular em comparação aos indivíduos sem dentes. O estudo identificou que ter dentes está associado positivamente ao relato do uso regular dos serviços de saúde bucal entre os idosos.

A 4th-order single-loop Follow-the-Leader-Feedback (FLFB) low-pass filter is hereby presented. The outstanding FLFB noise behavior has been exploited to release a specific power budget for linearity performance enhancement. Moreover, two pairs of complex poles are synthesized by using a single compact Active-RC cell, avoiding cascade of two or more stages (typically needed for high order filters), and relaxing this way noise power constraints. A prototype of the filter has been integrated in CMOS 0.18μm technological node, having 22.5MHz -3dB low-pass frequency. 21.5dBm in-band IIP3 and 76μVRMS input referred in-band integrated noise have been achieved. The SNR for a -40dB-THD is 69dB. The power consumption is 7mA. The efficiency of the hereby proposed technique is demonstrated by the very high Figure-of-Merit (160J-1) achieved by the FLFB filter comparing with the Active-RC filters state-of-the-art.

A low power 7.5---10.6 GHz frequency synthesizer for impulse radio ultra-wide band (IR-UWB) is designed and fabricated in 65 nm CMOS technology. The synthesizer is based on an integer-N type-II 4th-order PLL architecture. A 7-bit voltage-controlled oscillator with 31 % tuning range and a set of high-speed dividers are used to synthesize all the carriers defined by the IEEE standard 802.15.4a. The frequency dividers are based on true single phase clock logic resulting in compact implementation and low power consumption. The 0.33 mm2 fully integrated synthesizer consumes 5.13 mA from a 1.2 V supply. With a 3-dB closed-loop bandwidth of 100 kHz, the settling time is 15 µs. It features

In this paper, a UHF-RFID power management circuit is presented. It is able to power body sensor networks nodes, starting from -25dBm UHF-RFID input signal power. It is based on an initial Dickson's RF-DC rectifier circuit, followed by an ultra-low-voltage integrated boost converter, realized in 180nm CMOS technology, that is used to further step-up of the rectified DC-voltage and to guarantee the RF-to-load isolation. Measurements demonstrate the ability of the power management circuit to provide 400mV output voltage when a -25dBm continuous wave at 866.5MHz (European UHF RFID frequency) is applied at the input. © 2015 IEEE.

A 4th-order single-loop follow-the-leader-feedback (FLFB) low-pass continuous-time filter in CMOS 0.18 μm is hereby presented. The outstanding FLFB noise behaviour is exploited to allocate the power consumption to linearity performance. The low-pass filter prototype features 22.5 MHz-3 dB frequency, 21.5 dBm-IIP3 and 76 μVRMS input referred in-band integrated noise. The overall power consumption is 7 mA from a 1.8 V supply voltage. The signal-to-noise ratio for a -40 dB-total harmonic distortion is 69 dB.

An improved Active-Gm-RC filter architecture is proposed in this paper. With respect to the biquad Active-Gm-RC cell, this architecture exploits the second pole of the Opamp to increase the filter order up to 3, while maintaining single Opamp topology. This reduces the required power per pole. A prototype of the low-pass filter has been designed in 28nm CMOS technology. The filter power consumption is 340μW with a 0.9V voltage supply, cut-off frequency is 150MHz achieving a Figure-of-Merit of 165dB.

This paper investigates the radiation tolerance of 28-nm bulk ${n}$ and ${p}$ MOSFETs up to 1 Grad of total ionizing dose (TID). The radiation effects on this commercial 28-nm bulk CMOS process demonstrate a strong geometry dependence as a result of the complex interplay of oxide and interface charge trapping relevant to the gate-related dielectrics and the shallow trench isolation. The narrowest/longest channel devices have the most serious performance degradation. In addition, ${n}$ MOSFETs present a limited on-current variation and a significant off-current increase, while ${p}$ MOSFETs show a negligible off-current change and a substantial on-current degradation. The postirradiation annealing annihilates or neutralizes oxide trapped positive charges and tends to partly recover the degraded device performance. To quantify the effects of TID and postirradiation annealing, parameters including the threshold voltage, the free carrier mobility, the subthreshold swing, and the drain-induced barrier lowering are extracted.

This paper proposes two fully-integrated cap-less (i. e. without external capacitor) preamplifiers for silicon microphones. Proper dc biasing of the preamplifier is obtained with two solutions to implement a large feedback resistance (in the GO range), based on a switched resistor and a transistor in the off state, respectively. Both solutions have been implemented in a 0.18-μm CMOS technology and consume 230 μW from a single 1.8-V power supply. Both preamplifiers achieve a flat frequency response between 20 Hz and 20 kHz with a programmable gain ranging from −6 dB to +18 dB, and an integrated input referred noise (IIRN) lower than −100 dBV. The achieved total harmonic distortion (THD) is lower than −100 dB and −80 dB for the switched-resistor and the off-transistor preamplifiers, respectively, independently of the gain and in spite of the single ended configuration.

This paper uses the simplified charge-based EKV MOSFET model for studying the effects of total ionizing dose (TID) on analog parameters and figures-of-merit (FoMs) of 28nm bulk MOSFETs. These effects are demonstrated to be fully captured by the five key parameters of the simplified EKV model. The latter are extracted from the measured transfer characteristics at each TID. Despite the very few parameters, both the simplified large- and small-signal models present an excellent match with measurements at all levels of TID. The impacts of TID on essential parameters, including the drain leakage current, the threshold voltage, the slope factor, and the specific current, are then evaluated. Finally, TID effects on the transconductance G m , the output conductance G ds , the intrinsic gain G m /G ds and the transconductance efficiency G m /Id are investigated.

This paper presents the results of an irradiation study on single transistors manufactured in a 28 nm high-k commercial CMOS technology up to 1 Grad. Both nMOSFET and pMOSFET transistors have been irradiated and electrical parameters have been measured. For nMOSFETs, the leakage current shows an increase of 2–3 orders of magnitude, while only moderate degradation for other parameters has been observed. For pMOSFETs, a more severe degradation of parameters has been measured, especially in the drain current. This work is relevant as the evaluation of a new generation of CMOS technologies to be used in future HEP experiments.