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In this paper, based on a wet etched silicon interposer, we propose a 2.5D assembly of two dimensional optical transceivers for 400 Gbps parallel optical interconnections. In this opto-electronic packaging, two dimensional optical matrix is formed as 250 μm in both the x -and y-directions by exploiting commercial opto-electronic arrays, and a compact optical interface is used to couple the light channels with fiber ribbons. Each quadrant of the optical matrix is connected with its CMOS IC part via impedance matched co-planner wave guides. The shortest traces between optics and CMOS ICs can be 300 μm, benefiting from flip-chip technology. The process flow of silicon interposer fabrication is illustrated. With flip-chip bonding, 25 Gbps 2D 16-channel receiver is assembled on the silicon interposer, and the sub-module, including the optical interface, is scaled down to 4 mm by 6 mm. In addition, the performance of this assembled module is fully characterized. Uniform and clear eye patterns are captured for all of the channels. Receiver sensitivities are also tested for all channels at 25.78 Gbps, 2 31-1 PRBS, with the variation less than 1.5 dB at error free operation.

Multiple memory stacks can be integrated with a processor chip in the silicon interposer technology (“2.5D” stacking). In 2.5D architecture, there are two different network layers for both coherence and memory traffic. The CPU layer is used for coherence Core-to-Core traffic, while the interposer layer is associated with Core-to-Memory blocks traffic regularly. A load balancing strategy balances the traffics on the two network layers and optimizes the resources utilization. In the aforementioned strategy, after detecting congestion in the CPU layer, packets can be moved to the interposer one. It can be concluded that this transferring encounters the bottleneck of the edge portion that is connected to memory blocks. In this paper, we propose a Controlled Load Balancing Mechanism (CLBM) which efficiently controls bottleneck in load balancing methods. As a result, the CLBM selects an appropriate network based on the destination address without comparing latencies of two networks. Moreover, a multicast fault-tolerant ring is introduced to propagate network congestion information. The experimental results showed that, as compared with the absence of load balancing method and traditional load balancing strategy, our CLBM strategy achieves 37.82% and 17.22% average latency improvements and 22.19% and 8.55% average total power with minor overhead.

Silicon interposer technology ("2.5D" stacking) enables the integration of multiple memory stacks with a processor chip, thereby greatly increasing in-package memory capacity while largely avoiding the thermal challenges of 3D stacking DRAM on the processor. Systems employing interposers for memory integration use the interposer to provide point-to-point interconnects between chips. However, these interconnects only utilize a fraction of the interposer's overall routing capacity, and in this work we explore how to take advantage of this otherwise unused resource. We describe a general approach for extending the architecture of a network-on-chip (NoC) to better exploit the additional routing resources of the silicon interposer. We propose an asymmetric organization that distributes the NoC across both a multi-core chip and the interposer, where each sub-network is different from the other in terms of the traffic types, topologies, the use or non-use of concentration, direct vs. Indirect network organizations, and other network attributes. Through experimental evaluation, we show that exploiting the otherwise unutilized routing resources of the interposer can lead to significantly better performance.