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This paper presents the first wirelessly synchronized multichip array (WSMA) in 65-nm CMOS. The proposed architecture makes use of a central wireless signal to synchronize an mm-wave array, eliminating the need for connecting wires between the array elements. Wireless injection locking of a single chip is successfully demonstrated, and a 3-dB linewidth of 400 Hz at a carrier frequency of 50 GHz is achieved (stability ratio of 8 ppb). In addition, a two-element WSMA with an array aperture greater than 20 wavelengths is demonstrated using the proposed transceiver architecture. The reported transceiver includes a receiving on-chip antenna, a low-noise amplifier, an injection-locked voltage-controlled oscillator, a buffer amplifier, an in-phase/quadrature generator, a phase shifter, a power amplifier, and a transmitting on-chip antenna. The chip is fabricated in a 65-nm CMOS process and occupies an area of 1.7 mm $\times 3.8$ mm. This paper sets the foundation for increasing the array aperture through wireless injection locking, extending traditional array systems into the high-resolution, narrow-beamwidth regime. [ABSTRACT FROM PUBLISHER]

Frequency pulling of an oscillator integrated in a quadrature phase-shift keying wireless transmitter degrades the performance of the wireless system. This paper analyses the behavior of an oscillator in the presence of coupling between the oscillator and a power amplifier or antenna. Symbol switching in the modulator will cause frequency shifts in the oscillator at the modulation frequency. A new architecture for a 120 GHz quadrature frequency generator with large tuning range and immunity against PA-VCO coupling is presented. Combining the output signals of two independent oscillators, the pulling effect is removed and the frequency generator can be integrated with a PA and an antenna on the same chip. This architecture also makes quadrature generation with large tuning range feasible at 120 GHz. The chip is fabricated in a 45 nm CMOS technology and shows a tuning range of 16.2 GHz (13.5 $$\%$$ ), a phase noise of $$-$$ 112 dBc/Hz @ 10 MHz offset and a phase error of 5 $$^\circ$$ (Volkaerts et al. in: IEEE Radio Frequency Integrated Circuits Symposium (RFIC), ). [ABSTRACT FROM AUTHOR]