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A 55-71-GHz fully integrated power amplifier (PA) using a distributed active transformer (DAT) is implemented in 90-nm RF/MS CMOS technology. The DAT combiner, featuring efficient power combination and direct impedance transformation, is suitable for millimeter-wave (MMW) PA design. Systematic design procedures including an impedance allocation plan, a compensation line, and a gain boosting technique are presented for the MMW DAT PA. The monolithic microwave integrated circuit (MMIC) performs a high and flat small-signal gain of 26 [+ or -] 1.5 dB from 55 to 71 GHz, which covers a full band for 60-GHz wireless personal area network applications. Using cascode devices and a DAT four-way power combination, the CMOS PA delivers 14.5-and 18-dBm saturated output power with 10.2% and 12.2% power-added efficiency under 1.8- and 3-V supply voltage, respectively, at 60 GHz. The maximum linear output power ([P.sub.1 dB]) is 14.5 dBm. To the best of our knowledge, the MMIC is the first demonstration of a V-band CMOS PA using a DAT combining scheme with highest linear output power among the reported 60-GHz CMOS PAs to date. Index Terms--CMOS, distributed active transformer (DAT), gain boosting, power amplifier (PA), V-band.

A compact and broadband 0.8-77.5-GHz passive distributed drain mixer using standard 0.13-[micro]m CMOS technology is presented in this paper. To extend the operation bandwidth, a uniform distributed topology is utilized for wideband matching. This paper also analyzes the device size and number of stages for the bandwidth of the CMOS distributed drain mixer. To optimize the conversion gain performance of the CMOS drain mixer, a gate bias optimization method is proposed and successfully implemented in the mixer design. This mixer consumes zero dc power and exhibits a measured conversion loss of 5.5 [+ or -] 1 dB from 0.8 to 77.5 GHz with a compact size of 0.67 x 0.58 [mm.sup.2]. The output 1-dB compression point is -8.5 dBm at 20 GHz. To best of our knowledge, this monolithic microwave integrated circuit has the widest operation bandwidth among CMOS wideband mixers to date with good conversion efficiency and zero dc power consumption. Index Terms--CMOS, distributed mixer, drain mixer, millimeter wave (MMW).

Sub-harmonic modulator and demodulator are presented in this paper using 0.13-[micro]m standard CMOS technology for millimeter-wave (MMW) wireless gigabit direct-conversion systems. To overcome the main problem of local oscillator (LO) leakage in direct-conversion systems, the sub-harmonically pumped scheme is selected in this mixer design. An embedded four-way quadrature divider is utilized in the sub-harmonic Gilbert-cell design to generate quadrature-phases LO signals at MMW frequency. For broadband applications, a broadband matching design formula is provided in this paper to extend the operational frequency range from 35 to 65 GHz. To improve the flatness of conversion loss at high frequency, high-impedance compensation lines are incorporated between the transconductance stage and LO switching quad of the Gilbert-cell mixer to compensate the parasitic capacitance. The sub-harmonic modulator and demodulator exhibit 6 [+ or -] 1.5 dB and 7.5 [+ or -] 1.5 dB measured conversion loss, respectively, from 35 to 65 GHz. For MMW wireless gigabit applications, the gigabit modulation signal test is successfully performed through the direct-conversion system in this paper. To our knowledge, this is the first demonstration of the MMW CMOS sub-harmonic modulator and demodulator that feature broadband and gigabit applications. Index Terms--CMOS, demodulator, direct conversion, millimeter wave (MMW), modulator, sub-harmonically pumped.

A 44-GHz monolithic microwave integrated circuit (MMIC) low-loss built-in linearizer using a shunt cold-mode high-electron mobility transistor (HEMT), based on the predistortion techniques, is presented in this paper. The proposed cold-mode HEMT linearizer can enhance the linearity of the power amplifier (PA) with a low insertion loss (IL < 2 dB), a compact die-size, and no additional dc power consumption. These advantages make the linearizer more suitable for millimeter-wave (MMW) applications. The physical mechanism of the gain expansion characteristics of the proposed linearizer is analyzed. A systematic design procedure for a low-loss linearizer is developed, which includes: 1) insertion loss minimization through a device-size selection and 2) linearity optimization through a two-tone test. To demonstrate the general usefulness of the proposed linearizer, the linearizer was applied to a two-stage 44-GHz MMIC medium PA and a commercial MMW PA module. After linearization, the output spectrum regrowth is suppressed by 7-9 dB. To keep the adjacent channel power ratio below -40 dBc, the output power has been doubled from 15 to 18 dBm at 44 GHz. The error vector magnitude of the 16-quadrature amplitude modulation signal can be reduced from 6.11% to 3.87% after linearization. To the best of our knowledge, this is the first multistage MMW PA with a low-loss built-in linearizer. Index Terms--Linearizer, millimeter-wave (MMW), monolithic microwave integrated circuit (MMIC), nonlinear, power amplifier (PA).

An E-band high image-rejection sub-harmonic in-phase/quadrature (IQ) modulator for a high-order quadrature amplitude modulation (QAM) signal is designed and implemented on standard 65-nm CMOS technology. To maintain high image-rejection ratio of the IQ modulator over a wide bandwidth for high data-rate application, a load-insensitive analysis and a local oscillator (LO) broadband 45^\circ power splitter are proposed to achieve low amplitude and phase imbalanced structure. In addition, the doubly balanced sub-harmonic Gilbert-cell mixer with the advantages of good LO leakage suppression has been selected in the mixer design. The IQ modulator demonstrates a measured flat conversion gain of 0 \pm 1 dB from 55 to 85 GHz. The image rejection ratio is better than 40 dBc from 64 to 84 GHz. For millimeter-wave communication applications, the IQ modulator is integrated with a four-stage power amplifier to form a direct-conversion transmitter. The measured conversion gain of the transmitter is 33 dB and the measured saturated power is 11 dBm. Via high image rejection and good LO suppression of the modulator, a 1024-QAM modulated signal with a data rate of 500 Mb/s and 1.7% error vector magnitude is successfully demonstrated at 65 GHz. [ABSTRACT FROM PUBLISHER]

An ultra-low-power consumption and ultra-low local oscillator (LO) power double-balanced down-conversion mixer using standard 90-nm CMOS technology is presented in this paper. By employing a weak inversion biasing technique in a source-driven topology, the proposed V-band mixer can operate at microwatt power consumption of 453 \mu\W and has an ultra low LO power of -\6 dBm. In addition, under 1.2-V standard supply voltage, the down-conversion mixer exhibits excellent conversion-gain flatness of \ 5.9\pm\ 1.5~\ dB and the measured LO-to-RF isolation is more than 37 dB from 53 to 70 GHz, and OP1 dB of -\9.2 dBm at RF frequency of 60 GHz. Based on aforementioned results, the presented monolithic microwave integrated circuit can mitigate power-hungry issues while providing reasonable RF performance, which is important for a low-power communication system. [ABSTRACT FROM AUTHOR]

A bandwidth-enhanced technique for a Miller divider is presented in this paper. The proposed frequency divider consists of a band-switched Miller divider and digital-assisted circuit to switch the resonator automatically. The proposed frequency divider is implemented in \0.18-\mu\ m CMOS technology and has a measured 57.4% bandwidth from 8.2 to 14.8 GHz at an input power of 0 dBm. The dc consumption is 12 mW. Compared to the previously reported Miller dividers, the proposed circuit achieves the widest fractional bandwidth. [ABSTRACT FROM AUTHOR]

In this paper, W-band flip-chip-assembled CMOS chip modules with transition compensation are presented, a three-stage amplifier, a balanced amplifier, and a down-converted Gilbert-cell subharmonic mixer are included in the chip set. The flip-chip process on ceramic integrated passive devices (CIPD) with a bump size of 30 \mum \,\times\,30 \mum \,\times\,27 \mum is developed for millimeter-wave applications. Without the flip-chip transition compensation, the frequency of the return loss of each chip is shifted, which deviates from the bare die measurement results. By applying the compensation network in the transition, the dips of the return loss are tuned back closer to the bare die measurement results. Moreover, a W-band amplifier flip-chip-assembled with a CPW-fed Yagi–Uda antenna on a CIPD and a W-band flip-chip-assembled receiver are presented for SiP integration. The effect of dicing edge variation is also included in the flip-chip model to achieve reasonable agreement between simulated and measured scattering parameters. To the best of our knowledge, this is the first demonstration of a CMOS chip set with flip-chip interconnects in the W-band for a system-in-package. [ABSTRACT FROM AUTHOR]