1. Building Time-Triggered Schedules for Typed-DAG Tasks with Alternative Implementations
- Author
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Zahaf, H. -E., Capodieci, N., Laboratoire des Sciences du Numérique de Nantes (LS2N), Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-École Centrale de Nantes (Nantes Univ - ECN), Nantes Université (Nantes Univ)-Nantes Université (Nantes Univ)-Nantes université - UFR des Sciences et des Techniques (Nantes univ - UFR ST), Nantes Université - pôle Sciences et technologie, Nantes Université (Nantes Univ)-Nantes Université (Nantes Univ)-Nantes Université - pôle Sciences et technologie, Nantes Université (Nantes Univ), and Università degli Studi di Modena e Reggio Emilia = University of Modena and Reggio Emilia (UNIMORE)
- Subjects
Real-time partitioning ,heterogeneous architecture ,unrelated ,preemption ,time-table ,[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR] ,FOS: Computer and information sciences ,Systems and Control (eess.SY) ,Electrical Engineering and Systems Science - Systems and Control ,Computer Science - Distributed, Parallel, and Cluster Computing ,FOS: Electrical engineering, electronic engineering, information engineering ,Distributed, Parallel, and Cluster Computing (cs.DC) ,[INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC] - Abstract
Hard real-time systems like image processing, autonomous driving, etc. require an increasing need of computational power that classical multi-core platforms can not provide, to fulfill with their timing constraints. Heterogeneous Instruction Set Architecture (ISA) platforms allow accelerating real-time workloads on application-specific cores (e.g. GPU, DSP, ASICs) etc. and are suitable for these applications. In addition, these platforms provide larger design choices as a given functionnality can be implemented onto several types of compute elements. HPC-DAG (Heterogeneous Parallel Directed Acyclic Graph) task model has been recently proposed to capture real-time workload execution on heterogeneous platforms. It expresses the ISA heterogeneity, and some specific characteristics of hardware accelerators, as the absence of preemption or costly preemption, alternative implementations and on-line conditional execution. In this paper, we propose a time-table scheduling approach to allocate and schedule a set of HPC-DAG tasks onto a set of heterogeneous cores, by the mean Integer Linear Programming (ILP). Our design allows to handle heterogeniety of resources, on-line execution costs, and a faster solving time, by exploring gradually the design space, arXiv admin note: text overlap with arXiv:1901.02450
- Published
- 2022