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3 results on '"Statically scheduled processors"'

1. AGAMOS: A Graph-Based Approach to Modulo Scheduling for Clustered Microarchitectures.

Author

Aletà, Alex, Codina, Josep M., Sánchez, Jesús, González, Antonio, and David Kaeli

Subjects
*COMPUTER architecture, *LOOP tiling (Computer science), *COMPUTER programming, *COMPUTER systems, *MICROPROCESSORS, *COMPUTER algorithms
Abstract

This paper presents AGAMOS, a technique to modulo schedule loops on clustered microarchitectures. The proposed scheme uses a multilevel graph partitioning strategy to distribute the workload among clusters and reduces the number of intercluster communications at the same time. Partitioning is guided by approximate schedules (i.e., pseudoschedules), which take into account all of the constraints that influence the final schedule. To further reduce the number of intercluster communications, heuristics for instruction replication are included. The proposed scheme is evaluated using The SPECfp95 programs. The described scheme outperforms a state-of-the-art scheduler for all programs and different cluster configurations. For some configurations, the speedup obtained when using this new scheme is greater than 40 percent, and for selected programs, performance can be more than doubled. [ABSTRACT FROM AUTHOR]

Published
2009
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2. AGAMOS: A Graph-Based Approach to Modulo Scheduling for Clustered Microarchitectures

Author

David Kaeli, Alex Aletà, Jesús Sánchez, Antonio González, Josep M. Codina, Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, and Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors

Subjects
ILP, Schedule, Speedup, Computer science, Modulo, Instruction replication, Processor scheduling, Statically scheduled processors, Parallel computing, Theoretical Computer Science, Scheduling (computing), Clustered microarchitectures, Microprocessors, Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC], Grafs, Teoria de, Graph partition, Workload, Graph theory, Microarchitecture, Computational Theory and Mathematics, Hardware and Architecture, Microprocessadors, Modulo scheduling, Heuristics, Software
Abstract

This paper presents AGAMOS, a technique to modulo schedule loops on clustered microarchitectures. The proposed scheme uses a multilevel graph partitioning strategy to distribute the workload among clusters and reduces the number of intercluster communications at the same time. Partitioning is guided by approximate schedules (i.e., pseudoschedules), which take into account all of the constraints that influence the final schedule. To further reduce the number of intercluster communications, heuristics for instruction replication are included. The proposed scheme is evaluated using the SPECfp95 programs. The described scheme outperforms a state-of-the-art scheduler for all programs and different cluster configurations. For some configurations, the speedup obtained when using this new scheme is greater than 40 percent, and for selected programs, performance can be more than doubled.

Published
2009

3. AGAMOS: A graph-based approach to modulo scheduling for clustered microarchitectures

Author

Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors, Aleta Ortega, Alexandre, Codina Viñas, Josep M., Sánchez Navarro, F. Jesús, González Colás, Antonio María, Kaeli, D, Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors, Aleta Ortega, Alexandre, Codina Viñas, Josep M., Sánchez Navarro, F. Jesús, González Colás, Antonio María, and Kaeli, D

Abstract

This paper presents AGAMOS, a technique to modulo schedule loops on clustered microarchitectures. The proposed scheme uses a multilevel graph partitioning strategy to distribute the workload among clusters and reduces the number of intercluster communications at the same time. Partitioning is guided by approximate schedules (i.e., pseudoschedules), which take into account all of the constraints that influence the final schedule. To further reduce the number of intercluster communications, heuristics for instruction replication are included. The proposed scheme is evaluated using the SPECfp95 programs. The described scheme outperforms a state-of-the-art scheduler for all programs and different cluster configurations. For some configurations, the speedup obtained when using this new scheme is greater than 40 percent, and for selected programs, performance can be more than doubled., Peer Reviewed, Postprint (published version)

Published
2009

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