Search

The redundancy in switching states to generate different voltage levels is of great importance to incorporate fault-tolerant features in multilevel inverters. However, this redundancy comes at the expense of high device count, which is paralleled with vulnerable characteristics of semiconductor devices, resulting in low reliability. About this concern, the present study introduces a novel fault-tolerant topology to generate the five-level output voltage. The proposed topology can tolerate open-circuit failure, for single and multiple switches with the help of novel redundant leg architecture and short-circuit condition is dealt with the fast fuses. The comparative study with recent literature is discussed, which reveals the superiority of the proposed topology, in terms of qualitative as well as quantitative parameters. Switching strategies are proposed under different single and multiple switch fault cases, which achieves self-balancing of capacitor voltage. Thus, no complex control scheme is required. The simulation is performed in MATLAB/Simulink, and the feasibility of the proposed topology is validated using experimental results.

Photovoltaic (PV) systems, especially which are installed in the remote areas, stand in need for a highly reliable system. A high failure rate of the semiconductor switches and capacitors yields a very low reliability of the inverters used in the PV system. Conventional two-level inverters are replaced by multilevel inverters (MLIs) to effectively improve the output quality waveform. However, MLIs incorporate a high device count in their architecture which further impairs the reliability of the PV system. Recent research has focused on developing fault-tolerant MLI topologies with reduced device count. However, the number of active devices and power losses, factors which are many of the times overlooked, are key in determining the reliability of the inverter. Here, the reliability of a novel fault-tolerant MLI topology is evaluated bearing in mind the effect of power losses on the junction temperature. Equal (or best) voltage source utilisation characteristics help in maintaining the uniform charge of the batteries. The concept of reliability is evaluated mathematically. The fault tolerance and even source utilisation of the proposed topology is verified through the obtained experimental results.

Multilevel inverters (MLIs) have developed deep roots in various industrial sectors owing to their advantages over conventional two-level inverters. However, the reliability of the semiconductor devices has been one of the major concerns for the proper functioning of MLI. Therefore, a novel fault-tolerant topology is proposed in this study. The proposed topology is capable to tolerate single- and multi-switch faults. It has lesser device count compared with the most recent work in the field. Moreover, it achieves inherent voltage balancing across capacitors. The proposed fault-tolerant topology is simulated in MATLAB/Simulink and validated experimentally.

In this study, two new structures of single-phase hybrid multilevel inverter are proposed for both symmetrical and asymmetrical configurations that can be employed in drives and control of electrical machines and connection of renewable energy sources. The proposed configuration uses a less number of semiconductor devices and DC sources as compared with conventional and newly developed topologies which lead to a reduction in cost and installation area. The proposed topology poses a vital advantage of self-voltage balancing of its capacitor voltage regardless of load type, load dynamics and modulation index. Also, the proposed topology is expanded in a cascaded fashion which reduces the complexity and improves the performance significantly. A wide range of comparison is done with conventional and newly developed topologies to show the superior performance of proposed topologies regarding a total number of switches and DC sources. The multi-carrier pulse-width modulation strategy is adopted for generating switching pulses for respective switches. A laboratory prototype is developed for testing the performance of the proposed topology for 9-level and 17-level inverters.

Reduced voltage stress and low-total harmonic distortion are the main causes for such widespread application of multilevel inverters (MLIs) in various industrial sectors. However, reliability is one of the major concerns of MLIs as it uses a large number of switches as compared with two-level inverters. Therefore, a newly developed transistor clamped H-bridge inverter is proposed in the literature which uses a relatively less number of switches and DC sources as compared with cascaded H-bridge but lacks in reliability due to the absence of redundant states. Hence, in this study, the reliability improvement strategy for newly developed five-level transistor clamped H-bridge-based cascaded inverter is proposed which can be generalised for any number of levels. In the proposed fault tolerant strategy, the fault can be broadly classified based on the two main legs of the proposed inverter. Moreover, the proposed fault tolerant strategy does not require any kind of external circuit for maintaining its capacitor voltage in the balanced state. Finally, to validate the concept, a laboratory prototype of the five-level inverter is developed and results are obtained successfully.

Low reliability is one of the major concerns of multilevel inverter due to the requirement of a large number of semiconductor devices as compared to two-level inverters. Thus, in this paper, a novel topology of multilevel inverter is proposed that can tolerate both open and short-circuit faults on its switches. The proposed topology also reduces dc sources and capacitors as compared to the conventional and recently proposed fault-tolerant topologies. Two types of solutions are provided in order to make the proposed topology fault tolerant; first provides a partial solution to fault, while the second provides a complete solution to fault. In addition, a novel switching strategy is proposed to reduce the amount of capacitor voltage ripples under normal and postfault conditions. Also, the proposed switching scheme offers an additional advantage of self-voltage balancing of its capacitor voltage both under normal as well as postfault conditions. To validate the proposed concepts, simulation and experimental analysis are carried out and different results are presented to show the viability of the proposed topology under normal operation, during fault and postfault conditions.

Multilevel inverter (MLI) is receiving remarkable recognition due to its reduced voltage stress across the power switches and low total harmonic distortion in output voltage. However, MLI incorporates large number of semiconductor switches and hence increases its complexity. In this study, new structures of symmetrical and asymmetrical MLI are proposed. The proposed structures offer reduced number of controlled switches, power diodes, capacitors and DC sources as compared with classical and recently proposed topologies in the line. Reduction of switch count, driver circuit and DC voltage sources reduces the size, cost, complexity and enhances overall performance. Moreover significant reduction in voltage stress across the switches can be achieved. A comparative analysis of proposed topologies with the classical topology and recently published topologies has been made in terms of controlled switches, power diodes, driver circuit requirement, DC voltage sources and blocking voltage. Multi-carrier pulse width modulation strategy is adopted for generating the switching pulses. The detailed simulation study of the proposed topology has been carried out using MATLAB/Simulink and feasibility of topology has been validated experimentally.

The interest in development of newer topologies of multilevel inverter has been increasing rapidly in past few years. Recently introduced topologies achieve higher number of output voltage steps with reduced number of switches, DC voltage sources, voltage stress across switches and losses as compared with the conventional topologies. In this study, a new structure of symmetrical multilevel inverter is proposed. The proposed structure offers reduced number of controlled switches, power diodes and DC sources as compared with classical and recently proposed topologies in the literature. Reduction of switch count and DC voltage sources reduces the size, cost, complexity and enhances overall performance. Proposed topology is capable of producing 7, 9 and 11 levels of output voltage with seven switches only. Moreover, significant reduction in voltage stress across the switches can be achieved. A comparative analysis of proposed topology with the conventional topology and recently published topologies has been made in terms of controlled switches, power diodes, driver circuit requirement, DC voltage sources and blocking voltage. Multi-carrier pulse-width modulation strategy is adopted for generating the switching pulses. Simulation study of the proposed topology has been carried out using Matlab/Simulink and feasibility of topology has been validated experimentally.

The retinoblastoma susceptibility gene RB-1 is a tumour suppressor gene that encodes a protein (Rb) that regulates the transition from the G1 phase to the S phase of the cell cycle. Inactivation of the Rb gene has been shown in a variety of human tumours, including breast, ovarian, hepatic, prostatic, and endometrial carcinomas. Although Rb protein is normally expressed in the nuclei of healthy cells, during carcinogenesis there is a partial or complete loss of nuclear expression. Recently, some reports have indicated aberrant cytoplasmic expression of Rb protein. However, little is known about its cytoplasmic expression and significance as a prognostic marker in canine mammary tumours (CMT). The present study was performed on 36 malignant CMT cases in order to assess the mutational status and prognostic significance of Rb in primary malignant CMT. We report an almost complete loss of nuclear expression of Rb protein with corresponding gain of aberrant cytoplasmic expression in basal/myoepithelial cells in CMT. Strikingly, our analysis reveals a significant positive correlation between survival time and cytoplasmic expression of Rb protein in basal cells. Moreover, cytoplasmic expression of Rb protein in basal cells was also correlated with tumour grade and stage.