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This paper proposes and analyzes a CMOS divide-by-8 injection locked frequency divider (ILFD) with a divide-by-2 ring oscillator stacked on a capacitive cross-coupled oscillator used as an LC divide-by-4 ILFD. The divide-by-8 ILFD in the TSMC $0.18~\mu \text{m}$ 1P6M CMOS process has a locking range from 15.5 GHz to 17.8 GHz at the power consumption of 10 mW. The varactorless divide-by-8 ILFD occupies a small area of $0.8044\times 0.72$ mm2. The ILFD can be used in divide-by-4 mode and has a locking range from 4.8 GHz to 10.6 GHz at the power consumption of 10.43 mW. The ring oscillator based frequency divider (FD) is designed with a pair of differential outputs so that the whole divide-by-8 ILFD provides differential output. The ring oscillator FD uses unbalanced component parameters to optimize the circuit performance and it supplies two unbalanced tail currents to the LC ILFD, which also provide unbalanced outputs despite the circuit topology is a symmetric one. The unbalanced approach offers design flexibility.

An X-band GaN HEMT oscillator implemented with the WIN 0.25 μm GaN HEMT technology is proposed. The oscillator consists of a HEMT amplifier with an LC feedback network with four-path inductors. With the supply voltage of VDD = 2 V, the GaN VCO current and power consumption of the oscillator are 10.8 mA and 21.6mW, respectively. The oscillator can generate single-ended signal at 8.82 GHz and it also supplies output power 1.24 dBm. At 1MHz frequency offset from the carrier the phase noise is 124.95 dBc/Hz. The die area of the GaN HEMT oscillator is 2×1 mm2.

This article presents and analyzes a wide-locking range divide-by-5 injection-locked frequency divider (ILFD) manufactured in the TSMC 0.18- $\mu \text{m}$ processes. The ILFD uses the balanced injection method and uses the pure harmonic mixing approach at low injection power, and it is designed with an RLC dual-resonance resonator. The harmonic mixer relies on the self-generated second harmonic, which increases with injection power. Because of no narrowband filter as used in the linear mixer counterpart, the divide-by-5 ILFD uses a wideband design method. In addition, the ILFD enhances the divide-by-5 locking range via the overlapped dual-band locking ranges as verified by both experiment and simulation. At the drain–source bias ${V} _{\text{DD}}$ of 0.8 V and at the incident power of 0 dBm, the locking range of the divide-by-5 ILFD is 3.6 GHz, from the incident frequency 13.0–16.6 GHz with the percentage 24.3%. The core power consumption is 4.09 mW, and the die area is $1.02\times0.93$ mm2.

This article designs and analyzes LC injection-locked frequency dividers (ILFDs) using dual-resonance LC resonator. The ILFD consists of two single-resonance LC -tank capacitive cross-coupled sub-ILFDs operating at 3.7 and 5.1 GHz, respectively, and the two sub-ILFDs are coupled by the electric field through a pair of metal–insulator–metal (MIM) capacitors. The die area in the Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.18- $\mu \text{m}$ CMOS is $0.65\times1.023$ mm2. By controlling the gate voltages of the switching transistors, the ILFD has three different operational modes—high-band dominant mode, low-band dominant mode, and concurrent oscillation mode. Overlapped locking range is demonstrated for the first time in the designed electric-field coupling resonator ILFD. Non-overlapped locking range is found for the ILFD manifesting an effect of the dual-resonance resonator.

This article designs and analyzes wide locking range (LR) high even-modulus LC -tank injection-locked frequency dividers (ILFDs) with current-reused topologies. The current-reused LC ILFD uses two stacked LC sub-ILFDs sharing the same dc current. The current-reused ILFD becomes a divide-by-4 ( $\div 4$ ) ILFD, when both sub-ILFDs are used $\div 2$ ILFDs, and it is used as a divide-by-8 ( $\div 8$ ) ILFD when one sub-ILFD is used a $\div 4$ ILFD. Both sub-ILFDs use nMOSFETs as linear injection mixers for high conversion gain. For the $\div 8$ LC ILFD designed in the TSMC 0.18- $\mu \text{m}$ CMOS process, the circuit uses one high-frequency $\div 4$ sub-ILFD and one low-frequency $\div 2$ sub-ILFD, at the supply of 1.6 V, and at the incident power of 0 dBm, the LR is 4 GHz (38.835%), from the incident frequency 8.3 to 12.3 GHz. The $\div 8$ ILFD core power consumption is 13.98 mW, and the die size is $1.2 \times 1.2$ mm2. Both the $\div 8$ LC ILFD and the $\div 4$ sub-ILFD have nonoverlapped and overlapped LRs, which are due to a dual-resonance resonator used in the varactor-free n-core sub-ILFD. The LC dual-resonance resonator is due to parasitic capacitors in active FETs and on-chip spiral inductors and inductive elements, and it is used to get wide overlapped LR. Two $\div 4$ LC ILFDs inherent in the designed circuit are also studied.

Distributed LC resonator and resistively distributed resonator belong to the same technique used to extend the locking range of injection-locked frequency divider (ILFD). ILFD using the former resonator often has one locking range, and extension of locking range is attributed to oscillation frequency increment. This paper measures and analyzes the input sensitivity of a CMOS ILFD with a resistively distributed resonator and with the divide-by-3 and divide-by-2 functions, and the input sensitivity shows a wide single-band locking range. The fabricated 0.18- $\mu \text{m}$ CMOS ILFD is made of a pair of cross-coupled n-type transistors, two direct-injection MOSFETs, and a resistively dual-resonance resonator. The wide single-band locking range of the designed ILFD is owing to the overlapped locking ranges, and it is verified by the smooth tuning range without forbidden region and nonoverlapped locking ranges measured on the same chip with the unbalanced injection structure. The frequency tuning is obtained with large tank resistance, which also reduces the frequency tuning hysteresis effect.

This paper studies the frequency tuning effect on the locking range property of a dual-resonance 3:1 injection-locked frequency divider (ILFD) fabricated in a foundry 0.18 μm BiCMOS process. The ILFD architecture is based on a capacitive cross-coupled oscillator in conjunction with a resistor-degraded dual-resonance resonator for the locking range improvement. At a power consumption of 5.26 mW and at injection power of P inj = 0 dBm the locking range from the measurement is from 6.2 to 12.6 GHz (68.09%). The frequency tuning range of the free-running ILFD shows a frequency tuning hysteresis effect; at low input power level the locking range shows bipolar locking ranges and at high injection power the locking range is independent of the measured voltage tuning direction.

This Letter proposes a divide-by-2 injection-locked frequency divider (ILFD) with a new passive resonator. The ILFD in the 0.18 μm 1P6M CMOS process uses a three-dimensional inductor consisted of three series single-path and multi-path inductors. Measured data shows that the varactor-less divide-by-2 ILFD has wide locking range, low power consumption and occupies a small area of 0.4446 × 0.9198 mm 2 .

A triple-band divide-by-2 LC injection-locked frequency divider (ILFD) was implemented in the TSMC 0.18 μm 1P6M CMOS process, and it uses a cross-coupled nMOS pair and two shunt 4th order LC resonators to form a 6th order resonator with three resonant frequencies. Measured data has shown that the ILFD has three locking ranges at fixed bias condition or by varactor bias switching.

A triple-band (TB) oscillator was implemented in the TSMC 0.18 ㎛ 1P6M CMOS process, and it uses a cross-coupled nMOS pair and two shunt 4 th order LC resonators to form a 6 th order resonator with three resonant frequencies. The oscillator uses the varactors for band switching and frequency tuning. The core current and power consumption of the high (middle, low)- band core oscillator are 3.59(3.42, 3.4) ㎃ and 2.4(2.29, 2.28) ㎽, respectively at the dc drain-source bias of 0.67V. The oscillator can generate differential signals in the frequency range of 8.04-8.68 ㎓, 5.82-6.15 ㎓, and 3.68-4.08 ㎓. The die area of the triple-band oscillator is 0.835 × 1.103 ㎟.

This study describes the design and operation principle of quadrature voltage-controlled oscillator (QVCO) with complementary current-reuse (CR) voltage-controlled oscillators (VCOs). One CR complementary metal-oxide semiconductor (CMOS) VCO consists of a pair of p-type metal-oxide semiconductor field-effect transistors (pMOSFETs) and n-type metal-oxide semiconductor field-effect transistors (nMOSFETs), and an inductor. The other CR VCO consists of a pair of pMOSFET and heterojunction bipolar transistors (HBTs), and one inductor. The two CR VCOs are used to construct differential VCOs, which are subsequently used to build QVCOs coupled via coupling networks. The Bipolar-CMOS (BiCMOS) VCO and QVCO have been implemented with the Taiwan Semiconductor Manufacturing Company, Limited (TSMC) 0.18 μm SiGe BiCMOS technology. The CMOS QVCOs have been implemented with the TSMC 0.18 μm CMOS process. The quadrature phase generation and oscillation frequency equations are derived based on the block diagram of QVCO circuit.

This paper reviews the use of capacitive cross-coupled oscillator in the design of wide locking-range injection-locked frequency dividers (ILFDs). The advantages of capacitive cross-coupled ILFDs as compared to direct cross-coupled ILFDs are lower power consumption and wider locking range. Experimental examples of CMOS divide-by-2, divide-by-3 and divide-by-4 ILFDs are used to demonstrate the RF performance improvement by using this circuit topology.

A 2.48 GHz class-C voltage controlled oscillator (VCO) without any dynamic back bias circuit is presented. The VCO uses three-path high Q-factor inductor as the low loss resonator and class-C cross-coupled nMOSFET pairs for high dc/RF conversion efficiency and direct cross-coupled pMOSFET for dc current reuse. At the supply voltage of 1.2 V, the core power consumption is 0.24 mW. The phase noise of the VCO is −124 dBc/Hz and the VCO figure of merit is −197.0 dBc/Hz. The VCO was implemented in the TSMC standard 0.18 μm SiGe BiCMOS process and occupies a die area of 0.799 × 0.809 mm2.

A 2.5 GHz Class-C voltage-controlled oscillator (VCO) with dynamic back-gate-biased MOSFET is proposed. A dynamic gate biasing circuit is used to reduce power consumption by switching N-type MOS from initial Class-AB to Class-C operation in steady state. Moreover, the VCO uses dynamic back-gate bias to reduce threshold voltage of switching MOSFET during the start-up oscillation. The Class-C differential VCO is implemented in TSMC 0.18 μm bipolar-complementary-metal-oxide-semiconductor (BiCMOS) process. The measured phase noise is -124.8 dBc/Hz at 1 MHz offset frequency from 2.48 GHz carrier while consuming 2.64 mW power from a 0.8 V supply. Tuning range of VCO is 0.72 GHz, from 2.48 to 3.3 GHz, whereas the control voltage was tuned from 0 to 2 V. The VCO occupies a chip area of 446 × 840 μm 2 and provides a figure of merit of -197.55 dBc/Hz.

Wide locking range is an important parameter for injection-locked frequency divider (ILFD) to cope with the supply voltage variation. This paper proposes a wide locking range divide-by-4 ILFD implemented in the TSMC 0.18 μm 1P6 M CMOS process. The ILFD uses a capacitive cross-coupled voltage-controlled oscillator as the core. The dc gate bias of cross-coupled FETs is smaller than dc drain bias to optimize the power and locking range. Dual-resonance LC resonator is also used to enhance the locking range. At the drain-source bias of 1.2 V, and at the incident power of 0 dBm the measured locking range of divide-by-4 ILFD is 3.3 GHz, from the incident frequency 7.5---10.8 GHz, the percentage is 36.06%. The core power consumption is 11.83 mW. The die area is 0.883 ? 0.851 mm2.

A triple-band and wide operation range divide-by-2 injection-locked frequency divider (ILFD) using a TSMC 0.18 μm 1P6 M CMOS technology is presented. The ÷2 ILFD circuit is realized with a cross-coupled n-core MOS LC-tank oscillator with a 6th order LC resonator constructed from three single-resonance parallel LC resonators. The core power consumption of the ILFD core is 11.6 mW at the supply voltage of 1 V. The free-running ILFD can operate at three frequency bands: 8.75, 5.79 and 3.7 GHz, and the ILFD operation range covers a high-band frequency range from 17.1 to 18.3 GHz, a middle-band from 10.1 to 12.7 GHz, and a low-band from 6.0 to 7.7 GHz. The band selection is obtained by tuning the varactor's control bias.

This paper exploits the application of dual-resonance LC resonator in the design of wide-locking-range injection-locked frequency dividers (ILFDs). The tail-injection and direct-injection divide-by-3 ILFD circuits in a standard CMOS process are realized with a pair of cross-coupled nMOSFETs with a dual-resonance LC-resonator. The locking range enhancement techniques such as linear mixer and quality-factor degradation are used to design wide-locking range divide-by-3 ILFD. At the incident power of 0 dBm the locking range of the divide-by-3 ILFD is 4.6 GHz (43.3 %), from the incident frequency 8.3 to 12.9 GHz.

Conventional CMOS injection-locked frequency dividers (ILFDs) were often designed with a single-resonance LC resonator and they have a single-band locking range. Wide-locking range in these ILFDs was obtained at the cost of lower output power. A triple-resonance (TR) resistor (R), inductor (L) and capacitor (C)-tank ILFD is presented to design a wide-locking range CMOS divide-by-2 circuit, which is based on a cross-coupled n-core MOS pair. The TR ILFD has three overlapped locking ranges seen as one-band locking range at high microwave injection power and it has large output power. At the core power consumption of 6.76 mW and at the microwave input power of 0 dBm, the divide-by-2 TR ILFD achieve a maximum locking range of 5.77 GHz (105.2%) from 2.6 to 8.37 GHz.

Over-voltage RF stress was applied to an LC dual-resonance injection-locked frequency divider (ILFD) to study the post-stress ILFD RF performance. The LC ILFD was implemented in the TSMC 0.18 μm 1P6M CMOS process and it was stressed at the supply voltage of 2.3 V for 5 h. The dual-resonance ILFD has dual-band locking ranges and it uses series-peaking injection MOSFET. The over-voltage RF stress reduces both the high-frequency and low-frequency band locking ranges. The ILFD current consumption can decrease or increase with stress time, and this depends upon the stress condition. The phase noise in the injection-locked state can decrease with stress time.

This paper, for the first time, investigates hot carrier effect on a divide-by-2 injection-locked frequency divider (ILFD). The ILFD was implemented in the TSMC 0.18 μm 1P6M CMOS process. The ILFD uses direct injection MOSFETs for coupling external signal to the series-resonant resonator. It is shown that the locking range decreases and the oscillation frequency increases with stress time, and the phase noise in both the free-running and locked state increases with stress time. The measured operation range after RF stress also shows degradation from the fresh circuit condition.

A new circuit technique is proposed to enhance the locking range of divide-by-3 injection-locked frequency dividers (ILFDs) implemented using a standard 0.18 μm CMOS process. The ILFD uses a transformer feedback to increase the second harmonic and enhances the conversion efficiency of injection metal–oxide semiconductor field-effect transistor mixers. The ILFD core consumes 10.8 mW power at the supply voltage of 0.9 V and with a circuit core current of 12 mA. At the incident power of 0 dBm, the measured locking range is 4.2 GHz (37.17%), from the incident frequency 9.2–13.4 GHz.

A novel wide locking range divide-by-4 injection-locked frequency divider (ILFD) is proposed in this paper and was implemented in the TSMC 0.18 μm 1P6 M CMOS process. The divide-by-4 ILFD uses a cross-coupled voltage-controlled oscillator with a parallel-tuned LC resonator and two mixers in series to serve as an injection device. At the drain-source bias of 0.8 V and at the incident power of 0 dBm, the locking range of the divide-by-4 is 1.7 GHz, from the incident frequency 10.3---12.0 GHz, and the percentage of locking range is 15.25 %. The core power consumption is 11.98 mW. At drain-source voltage of 0.9 V, the locking range of the divide-by-4 is 2 GHz, from the incident frequency 10.1---12.1 GHz, and the percentage is 18.0 %. At drain-source voltage of 1.0 V, the locking range is 2.2 GHz (20.0 %) from 9.9 to 12.1 GHz. The die area is 0.492 × 0.819 mm2.

A new wide locking range divide-by-3 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process is presented. The ILFD uses two concurrent injection mechanisms with two independent push---push circuits to extend the locking range. It is realized with a cross-coupled n-core MOS LC-tank oscillator. The core power consumption of the ILFD core is 11.496 mW. The divider's free-running oscillation frequency is tunable from 4.32 to 3.78 GHz by tuning the varactor's control bias, and at the incident power of 0 dBm the maximum locking range is 3 GHz (25 %), from the incident frequency 10.5 to 13.5 GHz. The operation range is 3.6 GHz (30.76 %), from 9.9 to 13.5 GHz.

A new wide locking range series-tuned (ST) divide-by-3 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process is presented. The ÷3 ILFD circuit is realized with a ST cross-coupled n-core MOS LC-tank oscillator. Two direct-injection MOSFETs in series are used as a frequency doubler and a dynamic linear mixer to widen the locking range. The power consumption of the ILFD core is 10.56 mW. The divider's free-running frequency is tunable from 3.529 to 3.828 GHz by tuning the varactor's control bias, and at the incident power of 0 dBm the maximum locking range is 2.3 GHz (21.6 %), from the incident frequency 9.5 to 11.8 GHz. The operation range is 2.5 GHz (23.7 %), from 9.3 to 11.8 GHz.

This letter proposes a high-performance CMOS dual-band voltage-controlled oscillator (VCO). The VCO consists of two cross-coupled VCOs coupled by a pair of switched inductors or LC resonators to vary the resonator's inductance. A pair of nMOSFET is used to switch high- and low-frequency bands. The VCO operates at the high-band using low resonator's inductance and the VCO operates at the low-band using large inductance. The proposed VCO has been implemented with the TSMC 0.18 μm 1P6M CMOS technology and it can generate differential signals in the frequency range of 5.6---6.66 GHz and 4.13---4.75 and it also has comparable high output voltage swings at both low and high-frequency bands. The die area of the dual-band VCO is 0.84 × 1.1 mm2. At the supply voltage of 0.75 V, the high (low)-band figure of merit is ?193.6 (?192.3) dBc/Hz.

This paper presents a complementary metal-oxide- semiconductor (CMOS) difierential voltage-controlled oscillator (VCO) implemented with the push-push principle. The push-push VCO uses two frequency doublers stacked in series with an LC quadrature voltage-controlled oscillator (QVCO) to share the dc current with the QVCO for low power consumption. The proposed CMOS VCO has been implemented with the TSMC 0.18"m CMOS technology, and the die area is 0:822£1:564mm 2 . At the supply voltage of 0.9V, the total power consumption is 3.15mW. The free-running frequency of VCO is tunable from 10GHz to 11.15GHz as the tuning voltage is varied from 0.0V to 1.2V. The measured phase noise at 1MHz frequency ofiset is i114:93dBc/Hz at the oscillation frequency of 9.99GHz, and the flgure of merit (FOM) of the proposed VCO is i190:0dBc/Hz.

This paper presents a new three-phase LC-ring voltage controlled oscillator (VCO) using the TSMC 0.18"m 1P6M CMOS process. The VCO consists of three single-ended complementary Colpitts VCOs coupled via a varactor ring. Tuning range of VCO is 0.59GHz, from 8.22GHz to 8.81GHz, while the control voltage was tuned from 0V to 1.1V and the VCO core power consumption is 2.82mW at the supply voltage of 1.1V. The measured phase noise is i118:14dBc/Hz at 1MHz ofiset frequency from 8.40GHz. The VCO occupies a chip area of 1:018£0:74mm 2 and provides a flgure of merit of i192:14dBc/Hz.

This paper presents a new quadrature voltage-controlled oscillator (QVCO), which consists of two p-core Colpitts cross-coupled voltage-controlled oscillators (VCOs) with an LC ring resonator to provide the quadrature outputs. The proposed CMOS QVCO has been implemented with the TSMC 0.18"m CMOS technology and the die area is 0:478£0:82mm 2 . At the supply voltage of 1.5V, the total power consumption is 20.4mW. The free-running frequency of the QVCO is tunable from 9.69GHz to 10.52GHz as the tuning voltage is varied from 0.0V to 2V. The measured phase noise at 1MHz frequency ofiset is i122:41dBc/Hz at the oscillation frequency of 10.52GHz and the flgure of merit (FOM) of the proposed QVCO is i189:7dBc/Hz.

A novel wide-locking range divide-by-3 injection-locked frequency divider (ILFD) is designed and fabricated in a standard 0.18 μm CMOS process. The CMOS ILFD uses a class-C capacitive cross-coupled oscillator as the core. It has been found that the locking range of the ILFD is enhanced when the DC-gate bias is smaller than the drain bias in the cross-coupled pair. At the supply voltage of 1.8 V, the core power consumption of the ILFD core is 10.7 mW. At the incident power of 0 dBm, the maximum locking range is 3.3 GHz (24.17%), from the incident frequency 12–15.3 GHz. At the incident power of 0 dBm, the operation range is 4.8 GHz (37.2%), from the incident frequency 10.5–15.3 GHz.

An enhanced locking range technique for a CMOS injection-locked frequency divider (ILFD) is presented, which uses a cross-coupled oscillator with a dual-resonance RLC resonator. This ILFD has dual locking ranges at a fixed bias, and the resistor in the resonator is used to have overlapping dual locking ranges so that a single-band wide-locking range is obtained. At the incident power of 0 dBm, the locking range of the divide-by-2 ILFD is 6.7 GHz, from 3 to 9.7 GHz, and the locking range percentage is 105.51%.

In this paper, we present a new and analytical drain current model for submicrometer SOI MOSFET's applicable for circuit simulation. The model was developed by using a two-dimensional (2-D) Poisson equation, and considering the source/drain resistance and the self-heating effect. Using the present model, we can clearly see that the reduction of drain current with the parasitic series resistance and self-heating effect for typical SOI devices. We also can evaluate the impact of series resistance and self-heating effects. The accuracy of the presented model has been verified with the experimental data of SOI MOS devices with various geometries.

Based on nonpinned surface potential concept, in this paper we present a compact single-piece and complete I-V model for submicron lightly-doped drain (LDD) MOSFETs. The physics-based and analytical model was developed using the drift-diffusion equation and based on the quasi two-dimensional (2-D) Poisson equation. The important short-channel device features: drain-induced-barrier-lowering (DIBL), channel-length modulation (CLM), velocity saturation, and the parasitic series source and drain resistances have been included in the model in a physically consistent manner. In this model, the LDD region is treated as a bias-dependent series resistance, and the drain-voltage drop across the LDD region has been considered in modeling the DIBL effect. This model is smoothly-continuous, valid in all regions of operation and suitable for efficient circuit simulation. The accuracy of the model has been checked by comparing the calculated drain current, conductance and transconductance with the experimental data.

In this paper, we present a new, analytical, and physics-based drain current model for both submicrometer and deep submicrometer MOSFET's. The model was developed by starting from a two-dimensional (2D) Poisson equation and using the energy balance equation. Using the present model, we can clearly see that the drain current increases with decreasing channel length due to a larger average channel mobility at shorter channel length. The formulas for the saturation drain voltage and the drain current can be reduced to their corresponding well-known formulas in the submicrometer range. The accuracy of the presented model has been verified with the experimental data of metal-oxide-semiconductor (MOS) devices with various geometries.

A new divide-by-3 injection-locked frequency divider (ILFD) is proposed. The ILFD consists of a 7.6 GHz voltage controlled oscillator (VCO) and two transformers, which are in series with the cross-coupled transistors in the VCO for signal injection. The proposed CMOS ILFD has been implemented with the TSMC 0.13 m CMOS technology. At the supply voltage of 0.8 V, the core power consumption is 1.25 mW, and the free-running frequency of the ILFD is tunable from 7.2 to 7.87 GHz. At the input power of 0 dBm, the total divide-by-3 locking range is from 21.56 to 23.63 GHz as the tuning voltage is varied from 0.0 to 0.8 V. The phase noise of the locked ILFD output is lower than that of the free-running ILFD in the divide-by-3 mode.