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In this paper, we present techniques that can be used to answer the following two questions: 1) how many wafers need to be allocated per treatment to detect a given difference in a device performance metric and 2) how can one determine if a given treatment significantly improved a performance metric? The approach presented here does not make any assumptions regarding the shape of the distribution or the spatial dependency structure for the within-wafer performance measurements and remains applicable for a variety of performance metrics, such as mean, variance, and median. The analysis method can be used in decisions regarding the appropriateness of allocating half or quarter wafer splits to a treatment. Furthermore, the approach allows us to evaluate and compare within-wafer sampling strategies for comparing performance metrics from competing flows. Index Terms - Metrology, nonparametrics, power curves, process development, sample size, test of significance, Type I and II errors.

Process technology development constitutes a significant cost in manufacturing integrated circuits. In this paper, we present a model-based approach for developing new process technology rapidly and inexpensively, using the salicide process to demonstrate the concepts. This approach is applied to evaluate performance tradeoffs, to develop insight into the underlying process physics, to quantify the impact of the salicide process on the device and circuit performance, and to estimate the process variability. The key idea of this approach is to group a sequence of process steps into a process module, and build simple and accurate process models for the module. The paper also illustrates the use of this model-based approach in synthesizing optimal processes rapidly based on requirements, contributing to the reduction of technology development cost and cycle time.

This paper presents a process monitoring system, which is designed to be used for monitoring VLSIC and other multistage manufacturing processes. The proposed process monitor can 1) simultaneously detect a variety of out-of-control conditions, 2) quantify the magnitude of process change, and 3) be used to compute the probability of meeting specifications. Average run length simulations show that for a single-stage process, the monitor is at least as good as the Shewhart-CUSUM charts for detecting changes in the distribution of the monitored characteristics. For a multistage process, however, the Bayesian monitor can significantly reduce the detection time by using in-line correlation information from earlier stages. The monitor has been applied to data from a state-of-the-art fabrication facility, and the results are promising.

Run-to-run and supervisory control algorithms determine the equipment recipe to produce a desired output wafer state given the incoming wafer state and the current equipment model. For simple, low-dimensional equipment models, this problem is not difficult. However, when there are multiple responses for the system and the equipment models are nonlinear, automated synthesis of recipes is complicated by the potential for multiple solutions. While there are standard techniques for handling such inverse problems in general, each of these techniques is optimal only under certain conditions. We present a framework for performing automated synthesis of recipes that integrates database search, local optimization, and global optimization into a consistent methodology that is applicable to a wide range of equipment models and inversion problems in general. The integrated framework imposes quasi-continuity on the extracted recipes, is scalable to systems of high dimensionality, and can be optimized to minimize the expected synthesis time for any given problem. The framework has been implemented in a system that performs statistical optimization of CMOS transistor designs. The integrated framework provides a factor of 16 increase in performance over global optimization and a factor of three increase over exhaustive search and multiple starts of a local optimizer.