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Ubiquitous integrated circuit applications help the humanity to rapidly evolve by supporting electronics systems that are more and more assuming autonomous functions and decisions of important responsibility for the society. In this context, dealing with security, reliability, and power issues of integrated circuits is fundamental to ensure the operation of systems within reasonable levels of privacy, safety, and energy consumption. Exploiting body terminals of transistors in CMOS technology-based systems, this work contributes with new techniques dedicated to: (a) test circuits – just after fabrication – for detecting possible hardware Trojans inserted to maliciously compromise systems; (b) test circuits on the fly for detecting transient faults provoked by radiation effects or malicious attacks; and (c) perform body bias adaptation in systems aiming to optimize speed and power but also compensate threshold voltage alterations induced by aging, process, voltage, and temperature variations. Moreover, herein, ongoing and near-future related activities and insights are discussed as potential perspectives of this work.

National audience; This work reveals additional timing difficulties by which concurrent error detection (CED) schemes can experience to deal efficiently with transients. It shows previously-unknown error scenarios where short-duration single transient faults in combinational logic circuits succeed in erroneously inverting stored results but CED schemes fail in detecting even single soft errors. The paper demonstrates that typical CED code-based schemes for protecting logic circuits are not as capable as they have been claimed whether flip-flops are used to register the error signals, and so timing conditions are suggested for a more efficient use of them.

Recent deep-submicron technology-based ICs are significantly more vulnerable to transient faults. The arisen errors are thus also more critical than they have ever been before. This thesis presents a further novel benefit of the Quasi-Delay Insensitive (QDI) asynchronous circuits in terms of reliability: their strong natural ability to mitigate longduration transient faults that are severe in modern synchronous circuits. A methodology to evaluate comparatively the transient-fault effects on synchronous and QDI asynchronous circuits is presented. Furthermore, a method to obtain the transient-fault mitigation ability of the QDI circuits' memory elements (i.e., the C-elements) is also proposed. Finally, mitigation techniques are suggested to increase even more the Celements' transient-fault attenuation, and thus also the QDI asynchronous systems' robustness., Les technologies nanoélectroniques récentes font que les circuits intégrés deviennent de plus en plus vulnérables aux fautes transitoires. Les erreurs engendrées sont aussi plus critiques que jamais auparavant. Cette thèse présente un nouvel avantage en terme de fiabilité des circuits asynchrones quasi-insensibles aux délais (QDI) : Leurs fortes résistances naturelles aux fautes transitoires de longue durée qui sont graves pour les circuits synchrones actuels. Une méthodologie pour évaluer comparativement les effets des fautes transitoires sur les circuits synchrones et asynchrones QDI est présentée. En outre, une méthode pour obtenir la résistance aux fautes transitoires des éléments mémorisants spécifiques aux circuits QDI (les portes de Muller) est également proposée. Enfin, des techniques de tolérance ont été étudiées pour augmenter encore la robustesse des portes de Muller aux fautes transitoires, et donc aussi la robustesse des systèmes asynchrones QDI.