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541 results on '"PACS 85.42"'

1. NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS

Author: Pavanello, Fabio, Marchand, Cédric, O'Connor, Ian, Orobtchouk, Régis, Mandorlo, Fabien, Letartre, Xavier, Cueff, Sébastien, Vatajelu, Ioana, Di Natale, Giorgio, Cluzel, Benoit, Coillet, Aurélien, Charbonnier, Benoit, Noé, Pierre, Kaván, František, Zoldak, Martin, Szaj, Michal, Bienstman, Peter, van Vaerenbergh, Thomas, Rührmair, Ulrich, Flores, Paulo, Guerra E Silva, Luis, Chaves, Ricardo, Silveira, Luis Miguel, Ceccato, Mariano, Gizopoulos, Dimitris, Papadimitriou, George, Karakostas, Vasileios, Brando, Axel, Cazorla, Francisco Javier, Canal, Ramon, Closas, Pau, Gusi Amigo, Adrià, Crovetti, Paolo Stefano, Carpegna, Alessio, Tzamn, Melendez Carmona, Di Carlo, Stefano, Savino, Alessandro, INL - Ingénierie et conversion de lumière (i-Lum) (INL - I-Lum), Institut des Nanotechnologies de Lyon (INL), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-École Supérieure de Chimie Physique Électronique de Lyon (CPE)-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS), INL - Conception de Systèmes Hétérogènes (INL - CSH), Architectures and Methods for Resilient Systems (TIMA-AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Laboratoire Interdisciplinaire Carnot de Bourgogne (ICB), Université de Technologie de Belfort-Montbeliard (UTBM)-Université de Bourgogne (UB)-Université Bourgogne Franche-Comté [COMUE] (UBFC)-Centre National de la Recherche Scientifique (CNRS), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Argotech a.s., Universiteit Gent = Ghent University (UGENT), Fakultät für Physik - Ludwig-Maximilians-Universität [München/Munich] (LMU), Ludwig-Maximilians University [Munich] (LMU), Instituto de Engenharia de Sistemas e Computadores (INESC), Department of Computer Science [Verona] (UNIVR | DI), Università degli studi di Verona = University of Verona (UNIVR), Department of Informatics and Telecomunications [Kapodistrian Univ] (DI NKUA), National and Kapodistrian University of Athens (NKUA), Barcelona Supercomputing Center - Centro Nacional de Supercomputacion (BSC - CNS), Universitat Politècnica de Catalunya [Barcelona] (UPC), Albora Technologies Limited [Barcelona], Department of Electronics and Telecommunications = DET Dipartimento di Elettronica e Telecomunicazioni [Politecnico di Torino] (DET), Politecnico di Torino = Polytechnic of Turin (Polito), Department of Computer Engineering (DAUIN), IEEE, and European Project: 101070238,HORIZON-CL4-2021-DIGITAL-EMERGING-01 ,NEUROPULS(2023)
Subjects: Signal Processing (eess.SP), FOS: Computer and information sciences, PACS 85.42, Hardware Architecture (cs.AR), FOS: Electrical engineering, electronic engineering, information engineering, modeling, Electrical Engineering and Systems Science - Signal Processing, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Computer Science - Hardware Architecture, simulation, artificial neural networks
Abstract: This special session paper introduces the Horizon Europe NEUROPULS project, which targets the development of secure and energy-efficient RISC-V interfaced neuromorphic accelerators using augmented silicon photonics technology. Our approach aims to develop an augmented silicon photonics platform, an FPGA-powered RISC-V-connected computing platform, and a complete simulation platform to demonstrate the neuromorphic accelerator capabilities. In particular, their main advantages and limitations will be addressed concerning the underpinning technology for each platform. Then, we will discuss three targeted use cases for edge-computing applications: Global National Satellite System (GNSS) anti-jamming, autonomous driving, and anomaly detection in edge devices. Finally, we will address the reliability and security aspects of the stand-alone accelerator implementation and the project use cases., Comment: 10 pages, 2 figures, conference
Published: 2023
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2. Langage et sémantique des expressions pour la synthèse de modèle Grafcet dans un environnement IDM

Author: Emmanuel Simeu, Maurice Tchuente, Gérard Nzebop Ndenoka, Université de Yaoundé I, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Laboratoire International de Recherche en Informatique et Mathématiques Appliquées (LIRIMA), Université de Yaoundé I-Université Badji Mokhtar - Annaba [Annaba] (UBMA)-Institut National de Recherche en Informatique et en Automatique (Inria)-Université Joseph Ki-Zerbo [Ouagadougou] (UJZK)-Université d'Antananarivo-Université Gaston Bergé Sénégal-Centre National de la Recherche Scientifique et Technologique (CNRST), Université de Yaoundé I-Université Badji Mokhtar Annaba (UBMA)-Institut National de Recherche en Informatique et en Automatique (Inria)-Université Joseph Ki-Zerbo [Ouagadougou] (UJZK)-Université d'Antananarivo-Université Gaston Bergé Sénégal-Centre National de la Recherche Scientifique et Technologique (CNRST), Reliable RF and Mixed-signal Systems (TIMA-RMS), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)
Subjects: Programming language, Computer science, Semantics (computer science), expressions Grafcet, Model synthesis, General Medicine, métamodèle, sémantique des expressions, [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE], computer.software_genre, grammaire hors-contexte, Ingénierie Dirigée par les Modèles, [INFO.INFO-CL]Computer Science [cs]/Computation and Language [cs.CL], [INFO.INFO-AU]Computer Science [cs]/Automatic Control Engineering, PACS 85.42, Ingénierie Dirigé}e par les Modèles, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, analyseur syntaxique, vérification de modèle, computer
Abstract: The GRAphe Fonctionnel de Commande Étapes Transitions (GRAFCET) is a powerful graphical modeling language for the pecification of controllers in discrete event systems.It uses expressions to express the conditions of transitions and conditional actions as well as the logical and arithmetic expressions assigned to stored actions. However, several research works has focused on the transformation of Grafcet specifications (including expressions) into control code for embedded systems. To make it easier to edit valid Grafcet models and generate code, it is necessary to propose a formalization of the Grafcet expression language permitting to validate its constructs and provide an appropriate semantics. For this, we propose a context-free grammar that generates the whole set of Grafcet expressions, by extending the usual grammars of logical and arithmetic expressions. We also propose a metamodel and an associated semantics of Grafcet expressions to facilitate the implementation of the Grafcet language. A parser of the expressions Grafcet emph G7Expr is then obtained thanks to the generator of parsers ANTLR, while the metamodel is implemented in the Eclipse EMF Model Driven Engineering (MDE) environment. The combination of the two tools makes it possible to analyze and automatically build Grafcet expressions when editing and synthesizing Grafcet models. Le GRAphe Fonctionnel de Commande Étapes Transitions (GRAFCET) est un puissant lan-gage de modélisation graphique pour la spécification de contrôleurs dans des systèmes à événe-ments discrets. Il fait usage des expressions pour exprimer les conditions de franchissement des transitions et des actions conditionnelles ainsi que les expressions logiques et arithmétiques assi-gnées aux actions stockées. Cependant, de nombreux travaux se sont penchés sur la transformation de spécifications Grafcet (y compris les expressions) en code de contrôle pour systèmes embar-qués. Pour faciliter l'édition de modèles Grafcet valides et la génération du code de contrôle, il est judicieux de proposer une formalisation du langage des expressions Grafcet, permettant de valider ses constructions et d'en pourvoir une sémantique appropriée. Pour cela, nous proposons une gram-maire hors-contexte qui génère tout l'ensemble des expressions Grafcet, en étendant les grammaires usuelles des expressions arithmétiques et logiques. Nous proposons également un métamodèle et une sémantique associée des expressions Grafcet pour faciliter la mise en oeuvre du langage Grafcet sous la forme d'un parseur des expressions Grafcet G7Expr obtenu grce au générateur d'analyseurs syntaxiques ANTLR, alors que le métamodèle est mis en oeuvre dans l'environnement d'Ingénie-rie Dirigée par les Modèles (IDM) Eclipse EMF. L'association des deux outils permet d'analyser et de construire automatiquement les expressions Grafcet lors de l'édition et la synthèse des modèles Grafcet.
Published: 2021

3. Leveraging Targeted Value Prediction to Unlock New Hardware Strength Reduction Potential

Author: Arthur Perais, System Level Synthesis (SLS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and BEN TITO, Laurence
Subjects: [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], micro architecture, speculation, Computer science, Pipeline (computing), general-purpose, Value (computer science), 02 engineering and technology, Parallel computing, Operand, 01 natural sciences, Footprint, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, high performance architecture, Fraction (mathematics), Rename, processeur généraliste, 010302 applied physics, micro-architecture, 020202 computer hardware & architecture, Microarchitecture, PACS 85.42, architecture hautes-performances, Hardware_CONTROLSTRUCTURESANDMICROPROGRAMMING, Instruction-level parallelism, spéculation
Abstract: International audience; Value Prediction (VP) is a microarchitectural technique that speculatively breaks data dependencies to increase the available Instruction Level Parallelism (ILP) in general purpose processors. Despite recent proposals, VP remains expensive and has intricate interactions with several stages of the classical superscalar pipeline. In this paper, we revisit and simplify VP by leveraging the irregular distribution of the values produced during the execution of common programs. First, we demonstrate that a reasonable fraction of the performance uplift brought by a full VP infrastructure can be obtained by predicting only a few "usual suspects" values. Furthermore, we show that doing so allows to greatly simplify VP operation as well as reduce the value predictor footprint. Lastly, we show that these Minimal and Targeted VP infrastructures conceptually enable Speculative Strength Reduction (SpSR), a rename-time optimization whereby instructions can disappear at rename in the presence of specific operand values.
Published: 2021

4. To Pin or Not to Pin: Asserting the Scalability of QEMU Parallel Implementation

Author: Frédéric Pétrot, Saverio Miroddi, Marie Badaroux, System Level Synthesis (SLS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Ticketsolve, ANR-18-CE46-0011,ImPreNum,Améliorer la prédictibilité des calculs numériques(2018), and ANR-19-P3IA-0003,MIAI,MIAI @ Grenoble Alpes(2019)
Subjects: discrete event simulation, parallel simulation, Reduced instruction set computing, Computer science, Binary translation, Parallel computing, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, Parsec, performance evaluation, Instruction set, ARM architecture, Parallel processing (DSP implementation), PACS 85.42, Scalability, Benchmark (computing), dynamic binary translation
Abstract: International audience; Due to its speed in cross-executing sequential code, dynamic binary translation is the unchallenged technology for full system-level simulation. Among the translators, QEMU has become the de facto solution. It introduced parallel host execution of the target cores a few years ago for the ARM instruction set architecture and this support is now also available, among others, for RISCV. Given the popularity of these instruction sets in multi and many-core systems, assessing the scalability of their parallel implementation makes sense. In this paper, we use a subset of the PARSEC benchmark to measure the execution time of QEMU's parallel implementation, to which we added the ability to pin a target processor to a host core or hardware thread. We report the results of a wealth of experiments we performed on a 16-core/32-thread x86-64 SMP machine. They show that the support of parallelism in QEMU scales well, and that, somewhat counter intuitively, pinning does not improve performance.
Published: 2021

5. Distance learning is not an online face-to-face – Observations in microelectronic education

Author: Olivier Bonnaud, Laurent Fesquet, Institut d'Électronique et des Technologies du numéRique (IETR), Nantes Université (NU)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Coordination Nationale de la Formation en Microélectronique (CNFM), Centre National de la Recherche Scientifique (CNRS), Circuits, Devices and System Integration (CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Centre Interuniversitaire de Micro-Electronique (CIME), Institut National Polytechnique de Grenoble (INPG), Université de Nantes (UN)-Université de Rennes 1 (UR1), Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), and Circuits, Devices and System Integration (TIMA-CDSI)
Subjects: 4. Education, distance learning, PACS 85.42, microelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract: International audience; Due to the pandemic in early 2020, the French government, like many others, decided to temporarily close the universities and asked the faculties to entirely focus on online education or e-learning. In a world where digital contents exponentially increase, this pandemic has been an opportunity to develop distance e-learning. Many politicians found a unique opportunity to decrease or even eliminate face-to-face teaching activities. In engineering, this experience has shown clear limits and weaknesses. This paper highlights several problems that raised in microelectronic education and good reasons to move back to face-to-face learning especially for the acquisition of know-how. Indeed, know-how is mandatory for engineers, masters and PhDs in science and technology and this will never be replaced by a virtual experience. Real practice is the necessary price to pay for meeting the technological challenges of the upcoming decade.
Published: 2021

6. Microarchitecture-aware Fault Models: Experimental Evidence and Cross-Layer Inference Methodology

Author: Brice Colombier, Vincent Beroulle, Ihab Alshaer, Paolo Maistri, Christophe Deleuze, Laboratoire de Conception et d'Intégration des Systèmes (LCIS), Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA), Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), ANR-11-LABX-0025,PERSYVAL-lab,Systemes et Algorithmes Pervasifs au confluent des mondes physique et numérique(2011), BEN TITO, Laurence, Laboratoires d'excellence - Systemes et Algorithmes Pervasifs au confluent des mondes physique et numérique - - PERSYVAL-lab2011 - ANR-11-LABX-0025 - LABX - VALID, and IDEX UGA - - UGA2015 - ANR-15-IDEX-0002 - IDEX - VALID
Subjects: fault injection, Computer science, micro-architecture, Distributed computing, Cyber-physical system, Inference, Hardware_PERFORMANCEANDRELIABILITY, Fault injection, Fault (power engineering), Microarchitecture, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], PACS 85.42, Cross layer, Code (cryptography), Fault analysis, ComputingMilieux_MISCELLANEOUS, [INFO.INFO-CR] Computer Science [cs]/Cryptography and Security [cs.CR]
Abstract: Fault injection attacks are considered one of the major threats to cyber-physical systems. The increasing complexity of embedded microprocessors involves complicated behaviours in presence of such attacks. Realistic fault models are required to study code vulnerabilities and be able to protect digital systems from these attacks. However, inferring fault models using only limited observations of faulty microprocessors is difficult. In this article, we present experiments that show the difficulty of characterizing and modelling the fault injection effects. From there, we propose a complete approach for fault analysis to build proper fault models at different system levels, which will help in designing suitable countermeasures at reasonable cost.
Published: 2021

7. Automated Dysfunctional Model Extraction for Model Based Safety Assessment of Digital Systems

Author: Philippe Roche, Jean-Marc Daveau, Tiziano Fiorucci, Giorgio Di Natale, STMicroelectronics [Crolles] (ST-CROLLES), Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and IEEE
Subjects: Finite-state machine, business.industry, Process (engineering), Computer science, media_common.quotation_subject, Hardware_PERFORMANCEANDRELIABILITY, Automation, Upset, Field (computer science), Reliability engineering, PACS 85.42, Safety assurance, Quality (business), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Quality assurance, media_common
Abstract: International audience; In the field of automatic quality or safety assurance level evaluation, this paper proposes the first approach towards the automation of the extraction processes of both the valid and faulty state machines within a System-on-a-Chip. The data automatically extracted by this method is a relevant input for behavioural modelization and FMEA analysis. The method is based on a semi-automated approach for the systematic extraction of failure modes of a digital design in the hypothesis of a single-event upset (SEU) or stuck-at in flip-flops. This procedure aims to enhance human driven failure analysis and provide inputs for RAMS frameworks in the process of quality assurance of complex devices. The main objective is to transport and apply RAMS methods and tools in the area of SoCs design. Experimental results have been conducted on an I2C - AHB system, laying the base for a complete and more complex analysis on an entire SoC.
Published: 2021

8. Efficient deep learning approach for fault detection in the semiconductor industry

Author: Andrade Porras, Liliana Lilibeth, Baumela, Thomas, Pétrot, Frédéric, Briand, David, Bichler, Olivier, Coppola, Marcello, System Level Synthesis (SLS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Laboratoire Intelligence Artificielle Embarquée (LIAE), Université Paris-Saclay-Département Systèmes et Circuits Intégrés Numériques (DSCIN), Laboratoire d'Intégration des Systèmes et des Technologies (LIST), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Laboratoire d'Intégration des Systèmes et des Technologies (LIST), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), ANR-19-P3IA-0003,MIAI,MIAI @ Grenoble Alpes(2019), System Level Synthesis (TIMA-SLS), Laboratoire d'Intégration des Systèmes et des Technologies (LIST (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Laboratoire d'Intégration des Systèmes et des Technologies (LIST (CEA)), BEN TITO, Laurence, MIAI @ Grenoble Alpes - - MIAI2019 - ANR-19-P3IA-0003 - P3IA - VALID, Département Systèmes et Circuits Intégrés Numériques (DSCIN), STMicroelectronics [Grenoble] (ST-GRENOBLE), and Ovidiu VERMESAN
Subjects: quantized neural networks, field-programmable-gate-arrays, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], deep learning, hardware acceleration of AI, HW/SW integration, wafer maps, [INFO.INFO-OH] Computer Science [cs]/Other [cs.OH], PACS 8542, classification, embedded artificial intelligence, PACS 85.42, high-level synthesis, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract: International audience; The semiconductor industry is a very cost sensitive industry and yield is key to profitability. The ability to analyse and detect the faulty parts at several 1nanufacturing steps is also very in1portant to ensure the quality of the delivered integrated circuits. Severa! factors as aligninents, shifts or 1nasks rotations can lead to errors during the front-end step (wafer fabrication), or others causes such as fingerprints, scratches and stains can cause cosmetic da.nage during the back-end step (Silicon packaging). Therefore , an automatic visual inspection is required to ensure that the parts are free of any defects. In this chapter, we focus specifically on classifying wafer maps according to predefined defaults. We propose a platform which ain1s al n1aking the classification process n1ore energy efficient, by n1eans of the interconnection of two hardware parts. The first one, the microprocessor STM32MP 1, is responsible for image pre-processing and for offloading inference to a dedicated hardware accelerator. The second one, the hardware accelerator, is i1nple1nented in a Xilinx Zybo Z7-20 FPGA and uses a quantized neural network model. Preliminary results show that, for this low throughput applications that has a limited number of classes, the solution presented in this article can classify in real-time with accuracy above 80% using limited resources.
Published: 2021

9. Integrated Wideband Millimeter-Wave Bias-Tee – Application to Distributed Amplifier Biasing

Author: Jean-Daniel Arnould, Mohamad El Chaar, Florence Podevin, Antonio Augusto Lisboa de Souza, Manuel J. Barragan, Sylvain Bourdel, Laboratoire de Radio-Fréquence et d'Intégration de Circuits (RFIC-Lab ), Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA), Universidade Federal da Paraiba (UFPB), Reliable RF and Mixed-signal Systems (RMS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)
Subjects: Physics, business.industry, Bandwidth (signal processing), Electrical engineering, Distributed amplifier, Hardware_PERFORMANCEANDRELIABILITY, Integrated circuit, law.invention, Bias tee, CMOS, Parasitic capacitance, law, PACS 85.42, Broadband, Hardware_INTEGRATEDCIRCUITS, Wideband, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, ComputingMilieux_MISCELLANEOUS
Abstract: A wideband fully-integrated bias-tee well suited for millimeter waves is presented. Compared to conventional bias-tees, where RF-choke is optimized on the basis of its inductance value, here, the proposed RF-choke takes advantage of its low parasitic capacitance as one of the design parameters. While enabling wideband operation, in particular towards lower frequencies, this bias-tee enables ease-of-implementation, robustness against resonance, efficient power delivery to the intended wideband circuit and contributes to circuit area reduction on integrated circuit (IC) implementation. As a proof-of-concept, a wideband CMOS distributed amplifier (DA) with a lower-corner frequency (F lower ) of 5 GHz and an upper-corner frequency (F upper ) close to 100 GHz is implemented in STMicroelectronics’ 55-nm technology with the proposed bias-tee connected to its artificial drain line. The implemented bias-tee enabled a bandwidth close to 100 GHz and its RF-choke required a surface area of 82 µm x 82 µm. When integrated along with the DA, the overall chip area remained the same (0.89 mm2). Post-layout simulations showed a DC power overhead (due to inclusion of the on-chip bias-tee) limited to 17% of the DA-only consumption.
Published: 2021

10. Secure Test with RSNs: Seamless Authenticated Extended Confidentiality

Author: Michele Portolan, Paolo Maistri, Vincent Reynaud, Regis Leveugle, Architectures and Methods for Resilient Systems (TIMA-AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), European Project: 172930120,PENTA,RECHADESTIMD,HADES(2017), Architectures and Methods for Resilient Systems (AMfoRS ), BEN TITO, Laurence, and Hierarchy-Aware and secure embedded test infrastructure for Dependability and performance Enhancement of integrated Systems - HADES - - PENTA2017-04-01 - 0000-00-00 - 172930120 - VALID
Subjects: RSN, Authentication, Computer science, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, media_common.quotation_subject, SIB, Intellectual property, Computer security, computer.software_genre, confidentiality, Domain (software engineering), Test (assessment), IEEE 1687, Debugging, PACS 85.42, secure test, authentication, Confidentiality, State (computer science), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, computer, Testability, media_common
Abstract: International audience; The testability of electronic devices is of critical importance and it is often supported by IEEE standards. The presence of test structures, on the other hand, paves the way for malicious attackers to access the circuit and extract confidential knowledge such as secret keys or intellectual property. Removing the access to these structures after manufacturing test may prevent security breaches, but this solution is not definitive and excludes the possibility of advanced uses such as online debugging, diagnosis of designs and on-line updates or monitoring. For this reason, it is important to maintain the test infrastructure but to protect it against threats either external (e.g., attackers) or internal (e.g., hardware trojans). This can be achieved through protocols ensuring authentication added to confidentiality capabilities. In the case of Reconfigurable Scan Networks (RSN - IEEE 1687), some solutions currently exist, but are limited to external threats. In this paper, we review the recent state of the art in the domain, and present a novel solution addressing in a comprehensive and low-cost manner authentication and confidentiality, both inside and outside the device.
Published: 2021

11. Analysis and mitigation of timing inaccuracies in high-frequency on-chip sinusoidal signal generators based on harmonic cancellation

Author: Manuel J. Barragan, Ankush Mamgain, Salvador Mir, Reliable RF and Mixed-signal Systems (RMS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)
Subjects: Signal generator, Noise (signal processing), Computer science, Silicon on insulator, Linearity, Integrated circuit, law.invention, Harmonic analysis, law, PACS 85.42, Limit (music), Electronic engineering, Key (cryptography), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract: On-chip sinusoidal signal generators are a key element for enabling a wide variety of DfT and BIST applications for AMS-RF integrated circuits. Harmonic cancellation techniques have been recently proposed for the efficient implementation of high-quality embedded sinusoidal signal generators. However, harmonic cancellation techniques, based on phase-shifting and combining a set of periodic signals, rely on precise and accurate phase-shift control which makes them very sensitive to timing issues due to mismatch, noise, etc. Timing issues can severely limit the performance of these generators especially in high-frequency applications where precise timing becomes challenging. In this paper, we analyze the effects of timing inaccuracies on high-speed harmonic cancellation generators and we propose circuit techniques for mitigating them. Electrical simulation results on a 1.45 GHz sinusoidal signal generator implemented in ST 28 nm FDSOI technology are provided to validate our proposals.
Published: 2021

12. Identification of Hardware Devices based on Sensors and Switching Activity: a Preliminary Study

Author: Honorio Martin, Giorgio Di Natale, Elena Ioana Vatajelu, Universidad Carlos III de Madrid [Madrid] (UC3M), Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and IEEE
Subjects: Computer science, business.industry, 02 engineering and technology, Large range, Temperature measurement, 020202 computer hardware & architecture, Identification (information), Feature (computer vision), PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, 020201 artificial intelligence & image processing, Process variability, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Field-programmable gate array, business, Computer hardware, Voltage
Abstract: This work has been partially funded by the CNRS INS2I PUF2IOT 2020 projet and the UC3M program: Ayudas para la Movilidad del Programa Propio de Investigacion; International audience; Hardware device identification has become an im- portant feature for enhancing the security and the trust of interconnected objects. In this paper, we present a device iden- tification method based on measuring physical and electrical properties of the device, while controlling its switching activity. The method is general an applicable to a large range of devices from FPGAs to processors, as long as they embed sensors (such as temperature and voltage) and their measurements are available. The method is enabled by the fact that both the sensors and the effects of the switching activity on the circuit are uniquely affected by manufacturing-induced process variability. The device identification based on this method is made possible by the use of machine learning. The efficiency of the method has been evaluated by a preliminary study conducted on eleven FPGAs.
Published: 2021

13. Scramble Cache: An Efficient Cache Architecture for Randomized Set Permutation

Author: Thomas Hiscock, Giorgio Di Natale, Amine Jaamoum, Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), IEEE, and Architectures and Methods for Resilient Systems (TIMA-AMfoRS )
Subjects: 010302 applied physics, Computer science, CPU cache, business.industry, Cache-only memory architecture, Context (language use), 02 engineering and technology, 01 natural sciences, 020202 computer hardware & architecture, Set (abstract data type), Overhead (business), PACS 85.42, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Key (cryptography), Side channel attack, Cache, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Computer network
Abstract: This work was funded thanks to the French national program ”Programme d’Investissement d’Avenir IRT Nanoelec” ANR-10-AIRT-05.; International audience; Driven by the need of performance-efficient computations, a large number of systems resort to cache memories. In this context, cache side-channel attacks have been proven to be a serious threat for many applications. Many solutions and countermeasures exist in literature. Nevertheless, the majority of them do not cope with the constraints and limitations imposed by embedded systems. In this paper, we introduce a novel cache architecture that leverages randomized set placement to defeat cache side-channel analysis. A key property of this architecture is its low impact on performance and its small area overhead. We demonstrate that this countermeasure allows protecting the system against known cache side-channel attacks, while guaranteeing small overheads, making this solution suitable also for embedded systems.
Published: 2021

14. Local Clock Glitching Fault Injection with Application to the ASCON Cipher

Author: Paolo Maistri, Sriram Sankaran, G Surya, Amrita Center For Cyber Security Systems and Network (Amrita University), Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)
Subjects: business.industry, Computer science, End user, Locality, 020206 networking & telecommunications, 02 engineering and technology, Digital clock manager, Fault injection, Fault (power engineering), ASCON, Cipher, fault injection attack, Embedded system, PACS 85.42, lightweight cryptography, 0202 electrical engineering, electronic engineering, information engineering, 020201 artificial intelligence & image processing, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Field-programmable gate array, clock glitching, Throughput (business)
Abstract: International audience; Lightweight ciphers such as ASCON facilitate ease of implementation as well as provide better performance over conventional ciphers, thus making it suitable for resource-constrained devices. However, hardware implementations of these ciphers are vulnerable to a multitude of physical attacks (such as fault injections) requiring dedicated countermeasures thus causing a negative impact on security, performance and power consumption. Modeling and understanding the impact of these attacks on cipher operations and end users is mandatory. Further, detection and mitigation of such fault injection attacks is challenging due to the interconnected nature of cipher design, coupled with the varying number of possible design choices and with the forced trade-offs that need to be done in order to implement expensive countermeasures at the lowest possible cost. In this work, we aim to model a fault injection attack on ASCON and analyze its impact on FPGA. In particular, we implement the ASCON cipher and propose a methodology for fault injection attacks using synchronous clock glitching by Digital Clock Manager (DCM) introducing a novel approach of locality, which can be exploited to emulate general delay faults on focused parts of the design, such those induced by pulsed EM injections.
Published: 2020

15. Assessment of Machine Learning Algorithms for Near-Sensor Computing Under Radiation Soft Errors

Author: M. Garay Trindade, Rafael Garibotti, Luciano Ost, M. Letiche, R. Possamai Bastos, J. Beaucour, Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Pontifícia Universidade Católica do Rio Grande do Sul [Porto Alegre] (PUCRS), Loughborough University, Institut Laue-Langevin (ILL), ILL, This work has been partially supported by: IRT Na- noelec (ANR-10-AIRT-05) and LabEx PERSYVAL-Lab (ANR-11-LABX-0025-01), both funded by the French government program 'Investissement d’avenir', and MultiRad project funded by Région Auvergne-Rhône-Alpes’s international ambition pack., Partly supported by Persyval project ANR-11-LABX-0025-01 and by MultiRad project (évaluation des effets des radiations cosmiques dans des systèmes informatiques multi-coeurs d'applications critiques) funded by Région Rhône-Alpes's international Ambition Pack, and ANR-11-LABX-0025,PERSYVAL-lab,Systemes et Algorithmes Pervasifs au confluent des mondes physique et numérique(2011)
Subjects: Complex data type, 021103 operations research, 010308 nuclear & particles physics, business.industry, 0211 other engineering and technologies, Automotive industry, Cloud computing, 02 engineering and technology, Fault injection, Radiation, Machine learning, computer.software_genre, 01 natural sciences, Upset, Support vector machine, PACS 85.42, 0103 physical sciences, Artificial intelligence, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Aerospace, business, computer, Algorithm, ComputingMilieux_MISCELLANEOUS
Abstract: International audience; Machine learning (ML) algorithms have been regaining momentum thanks to their ability to analyze substantial and complex data, supporting artificial intelligence decisions in cloud computing but also in near-sensor computing in endpoint devices. Both cloud and near-sensor computing are liable to radiationinduced soft errors, especially in automotive and aerospace safety-critical applications. In this regard, this paper contributes by comparing the accuracy of tw o prominent machine learning algorithms running on a lowpow er processor upset by radiation-induced soft errors. Both ML algorithms have been assessed w ith the help of a fault injectionbased method able to natively emulate soft errors directly in a development board. In addition, neutron radiation test results suggest the most critical situations in w hich mitigation solutions should address.
Published: 2020

16. A Non-Closed-Form Mathematical Model for Uniform and Non-Uniform Distributed Amplifiers

Author: Antonio Augusto Lisboa de Souza, Manuel J. Barragan, Sylvain Bourdel, Florence Podevin, Mohamad El Chaar, Laboratoire de Radio-Fréquence et d'Intégration de Circuits (RFIC-Lab ), Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA), Reliable RF and Mixed-signal Systems (RMS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)
Subjects: computational modeling, bandwidth, Power gain, Computer science, 020208 electrical & electronic engineering, Bandwidth (signal processing), Semiconductor device modeling, Distributed amplifier, distributed amplifier, analytical model, 020206 networking & telecommunications, Context (language use), gain, 02 engineering and technology, BiCMOS, Artificial transmission line, CMOS, PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, semiconductor device modeling, mathematical model
Abstract: International audience; A non-closed-form general mathematical model for CMOS distributed amplifier (DA) for broadband applications is presented. Contrary to the artificial transmission line (TL) assumption made in the conventional analytical models, the proposed model treats the DA as a discrete set of cells connected together, and hence considers propagation and mismatch between inter-cells. This approach provides designers with a much more accurate first sizing of the DA compared to conventional ways and, as a result, leads to a reduced design time and complexity. The model enables both quantitative and qualitative analysis of a DA, for the purpose of aiding the designers in predicting the relations between DA performance and its multi-design parameters, especially in the context of non-uniform designs. In addition, it is well suited to Computer-Automated Design (CAutoD), to help in achieving designs having a given set of performance goals. The validation of the model is demonstrated on two designs, by a comparison with simulations done in Keysight's ADS tool and using STMicroelectronics' 55-nm SiGe BiCMOS design kit. First design is inspired from an already published non-uniform DA design while second one proposes a 100-GHz bandwidth CMOS uniform DA with 8 dB of power gain, after using it in a CAutoD process.
Published: 2020

17. Miniaturization of Transmission Lines: Meandered Slow-wave CPWs

Author: Tadeu Mota-Frutuoso, Emmanuel Pistono, Manuel J. Barragan, Christophe Gaquiere, Marc Margalef-Rovira, Philippe Ferrari, Loic Vincent, Abdelhalim A. Saadi, Laboratoire de Radio-Fréquence et d'Intégration de Circuits (RFIC-Lab ), Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA), Centre Interuniversitaire de Micro-Electronique (CIME), Institut National Polytechnique de Grenoble (INPG), Reliable RF and Mixed-signal Systems (TIMA-RMS), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA), Université catholique de Lille (UCL)-Université catholique de Lille (UCL), Puissance - IEMN (PUISSANCE - IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), This work has been funded by the European Union (ECSEL JU GA 737454: TowARds Advanced BiCMOS NanoTechnology platforms for RF applicatiOns -Taranto), and the General Directorate for Enterprises (DGE) in France., European Project: 737454,H2020,H2020-ECSEL-2016-1-RIA-two-stage,TARANTO(2017), and Reliable RF and Mixed-signal Systems (RMS )
Subjects: 010302 applied physics, Materials science, business.industry, CPW, 020206 networking & telecommunications, Ranging, transmission line, 02 engineering and technology, Dielectric, 01 natural sciences, Microstrip, Electric power transmission, CMOS, Transmission line, Q factor, PACS 85.42, 0103 physical sciences, mm-wave, 0202 electrical engineering, electronic engineering, information engineering, Miniaturization, Optoelectronics, slow-wave, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business
Abstract: International audience; This work presents novel transmission line structures based on Meandered Slow-wave CoPlanar Waveguides (MS-CPWs), aiming to achieve high miniaturization. As a proof-of-concept, these two kinds of transmission lines were designed and fabricated in the AMS 0.35 mu m CMOS technology together with classical straight and meandered microstrip lines. Measurement results from 70 kHz to 100 GHz of the fabricated transmission lines are presented. At 80 GHz, all the considered transmission lines present similar quality factors, ranging between 10 and 14. On the other hand, at this frequency, one of the developed MS-CPW presents an effective dielectric constant of 88, while the meandered microstrip exhibits an equivalent effective dielectric constant of 51, thus leading to higher compactness for the MS-CPW.
Published: 2020

18. VP Float: First Class Treatment for Variable Precision Floating Point Arithmetic

Author: Tiago Trevisan Jost, Christian Fabre, Albert Cohen, Yves Durand, Frédéric Pétrot, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), System Level Synthesis (TIMA-SLS), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Google Inc [Mountain View], Research at Google, ANR-18-CE46-0011,ImPreNum,Améliorer la prédictibilité des calculs numériques(2018), and System Level Synthesis (SLS )
Subjects: Coprocessor, Floating point, business.industry, Computer science, Interface (computing), variable precision arithmetic, Optimizing compiler, 010103 numerical & computational mathematics, Parallel computing, Supercomputer, computer.software_genre, 01 natural sciences, MPFR, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], Software, Memory management, LLVM, PACS 85.42, compilation, Compiler, Floating point arithmetic, 0101 mathematics, business, computer, compiler optimization
Abstract: International audience; Optimizing compilers for high performance computing only support IEEE 754 floating-point (FP) types and applications needing higher precision involve cumbersome memory management and calls to external libraries. We introduce an extension of the C type system to represent variable-precision FP arithmetic, supporting both static and dynamically variable precision. We design and implement a compilation flow bridging the abstraction gap between this type system and hardware FP instructions or software libraries. We demonstrate the effectiveness of our solution by enabling the full range of LLVM optimizations and leveraging two backend code generators: one for the ISA of a variable precision FP arithmetic coprocessor, and one for the MPFR multi-precision FP library. Both targets support the static and dynamically adaptable precision of our type system. On the PolyBench suite, our optimizing compilation flow targeting MPFR is shown to outperform the Boost programming interface for the MPFR library. CCS CONCEPTS • Software and its engineering → Source code generation; Imperative languages; Data types and structures; Dynamic compilers.
Published: 2020

19. Arbiterless Event-Based Imager Architecture with temporal and spatial redundancies suppression

Author: Laurent Fesquet, Nils Margotat, Mohamed Akrarai, Gilles Sicard, Circuits, Devices and System Integration (TIMA-CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), European Project: 783127,H2020-EU.2.1.1.7. - ECSEL,OCEAN12(2018), BEN TITO, Laurence, Opportunity to Carry European Autonomous driviNg further with FDSOI technology up to 12nm node - OCEAN12 - 2018-04-01 - 2021-12-31 - 783127 - VALID, and Circuits, Devices and System Integration (CDSI)
Subjects: Pixel, arbiterless image sensor, Event (computing), Computer science, business.industry, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 020208 electrical & electronic engineering, ComputingMethodologies_IMAGEPROCESSINGANDCOMPUTERVISION, 02 engineering and technology, frameless image sensor, Luminance, Kernel (image processing), PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, Redundancy (engineering), Computer vision, temporal and spatial redundancies suppression, Artificial intelligence, Image sensor, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Throughput (business), Energy (signal processing)
Abstract: International audience; We present a new image sensor architecture that manages spatial and temporal redundancies with an arbiterless readout and a pixel Address-Event Representation (AER) reading system. This frameless image sensor only generates few events over time in order to target an efficient power consumption compared to the commercial CMOS image sensors. Indeed, this image sensor does not generate anymore frames but events only when a change appears in the scene. Moreover, the event throughput depends on the luminance variations of the recorded scene. This means that more activity in the scene will generate more events and vice versa. Collecting events over a period of time will define an image. It is noticeable that, at each instant, the generated events characterize the zone of interest (the active area) of the scene. Consequently, processing such images should require less computing, communication and energy.
Published: 2020

20. From 1.8V to 0.19V voltage bias on analog spiking neuron in 28nm UTBB FD-SOI technology

Author: Ph. Galy, Lorena Anghel, V. Cincon, Elena Ioana Vatajelu, STMicroelectronics [Crolles] (ST-CROLLES), Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), SPINtronique et TEchnologie des Composants (SPINTEC), Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche Interdisciplinaire de Grenoble (IRIG), Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Grenoble Alpes (UGA), ANR-19-P3IA-0003,MIAI,MIAI @ Grenoble Alpes(2019), Architectures and Methods for Resilient Systems (TIMA-AMfoRS ), BEN TITO, Laurence, and MIAI @ Grenoble Alpes - - MIAI2019 - ANR-19-P3IA-0003 - P3IA - VALID
Subjects: Spiking neural network, low power, Computer science, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 020208 electrical & electronic engineering, Transistor, Spice, artificial neuron, Silicon on insulator, 02 engineering and technology, 021001 nanoscience & nanotechnology, law.invention, spiking neural network, CMOS, Neuromorphic engineering, law, PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Artificial neuron, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, Voltage
Abstract: International audience; The emergence of new hardware-oriented algorithms for convolutional neural networks (CNNs) or spiking neural networks (SNNs) used for efficient data interpretation, made neuromorphic computing a very promising solution. SNNs are very attractive due to their particularly low power consumption. This paper presents a comprehensive analysis of an analog spiking neuron designed in 28 nm UTBB FD-SOI CMOS technology from STMicroelectronics. Thick oxide MOS transistors with regular VT are selected to perform a low power design enhanced by using sub-threshold bias. The neuron operation is presented and analyzed through SPICE simulations performed at 0.7 V nominal voltage bias. Several parameters control the shape of the neuron response, such as: the synaptic excitation, the spike duration, and the refractory period. The neuron under study was fabricated and characterized for bias voltages ranging from 1.8 V standard bias to the measured limit of 0.19 V. The full functionality of the analog spiking neuron in FD-SOI is demonstrated.
Published: 2020

21. A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System

Author: Michele Portolan, Ghislain Takam Tchendjou, Vincent Reynaud, Salvador Mir, Paolo Maistri, Emmanuel Simeu, Manuel J. Barragan, Regis Leveugle, Kalpana Senthamarai Kannan, Lorena Anghel, Renato S. Feitoza, Architectures and Methods for Resilient Systems (TIMA-AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Reliable RF and Mixed-signal Systems (TIMA-RMS), SPINtronique et TEchnologie des Composants (SPINTEC), Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche Interdisciplinaire de Grenoble (IRIG), Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Grenoble Alpes (UGA), European Project: 172930120,PENTA,RECHADESTIMD,HADES(2017), Architectures and Methods for Resilient Systems (AMfoRS ), and Reliable RF and Mixed-signal Systems (RMS )
Subjects: 010302 applied physics, Authentication, business.industry, Computer science, circuit-aging, Circuit Aging, Mixed signal testing, Embedded Test Instruments, Mixed-signal integrated circuit, 02 engineering and technology, ADCs, 01 natural sciences, automated test environment, 020202 computer hardware & architecture, Secure Access, Software, End-to-end principle, Embedded system, mixed-signal testing, Automated Test Environments, PACS 85.42, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business
Abstract: International audience; The disruptive potential of the IEEE 1687 standard does not come from a single innovation, but rather from its capacity of providing a unified framework where heterogeneous approaches can co-exist and interact. In this Special Session, we will present the complementary research activities performed in the TIMA laboratory covering different aspects of the standard (Mixed-Signal instrument testing, Embedded Aging Monitors and Test Access Securization), and their coordination thanks to the Manager-for SoC Test (MAST) software environment.
Published: 2020

22. mm-Wave Through-Load Switch for in-situ Vector Network Analyzer on a 55-nm BiCMOS Technology

Author: Christophe Gaquiere, Abdelhalim A. Saadi, Philippe Ferrari, Manuel J. Barragan, Sylvain Bourdel, Emmanuel Pistono, Marc Margalef-Rovira, Reliable RF and Mixed-signal Systems (RMS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Laboratoire de Radio-Fréquence et d'Intégration de Circuits (RFIC-Lab ), Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA), Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), Puissance - IEMN (PUISSANCE - IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), European Project: 737454,H2020,H2020-ECSEL-2016-1-RIA-two-stage,TARANTO(2017), Reliable RF and Mixed-signal Systems (TIMA-RMS), and Laboratoire commun STMicroelectronics-IEMN T1
Subjects: Materials science, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 7. Clean energy, law.invention, law, 3-dB slow-wave coupler, in-situ reflectometer, mm-wave, 0202 electrical engineering, electronic engineering, information engineering, Hardware_INTEGRATEDCIRCUITS, Insertion loss, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, NMOS logic, Load control switch, business.industry, 020208 electrical & electronic engineering, Bandwidth (signal processing), Transistor, 020206 networking & telecommunications, Biasing, switch, PACS 85.42, Power dividers and directional couplers, Optoelectronics, business, on-wafer calibration, Voltage
Abstract: International audience; In this paper, an innovative millimeter-wave (mm-wave) through-load switch for in-situ reflectometers and on-wafer calibration is proposed. This two-port device can switch between two states: (i) a through connection or (ii) a 50 Ω load for both of its ports. The through-load switch is composed of a 3-dB directional coupler and two nMOS transistors controlled through a biasing voltage applied to their gate. Measurement results of a 120-GHz 3-dB directional coupler are provided up to 145 GHz together with EM simulations and circuit-level simulations up to 220 GHz of the through-load switch. A wide bandwidth is obtained, from 73 GHz to 179 GHz, with limited insertion loss of 2 dB.
Published: 2020

23. Static linearity BIST for Vcm-based switching SAR ADCs using a reduced-code measurement technique

Author: Antonio Gines, Renato S. Feitoza, Manuel J. Barragan, Salvador Mir, Reliable RF and Mixed-signal Systems (RMS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Instituto de Microelectrónica de Sevilla (IMSE-CNM), Universidad de Sevilla-Centro Nacional de Microelectronica [Spain] (CNM)-Consejo Superior de Investigaciones Científicas [Madrid] (CSIC), European Project: 172930120,PENTA,RECHADESTIMD,HADES(2017), Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo, Reliable RF and Mixed-signal Systems (TIMA-RMS), and Universidad de Sevilla / University of Sevilla-Centro Nacional de Microelectronica [Spain] (CNM)-Consejo Superior de Investigaciones Científicas [Madrid] (CSIC)
Subjects: Computer science, Transistor, Linearity, Successive approximation ADC, Topology (electrical circuits), 02 engineering and technology, Converters, 020202 computer hardware & architecture, law.invention, Linearity test, law, PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Code (cryptography), Hardware_INTEGRATEDCIRCUITS, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Linearity testing
Abstract: International audience; This work presents a reduced-code strategy for the static linearity self-testing of Vcm-based successive-approximation analog to digital converters (SAR ADCs). These techniques take advantage of the repetitive operation of SAR ADCs for reducing the number of necessary measurements for static linearity testing. In this paper we discuss the application of these techniques for the Vcm-based SAR ADC topology and present a practical BIST implementation based on an embedded incremental ADC. Electrical simulation results at transistor level are presented to validate the feasibility of the proposed on-chip reduced-code static linearity test.
Published: 2020

24. Nonlinear Codes for Control Flow Checking

Author: Osnat Keren, Giorgio Di Natale, Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Faculty of Engineering [Israel], and Bar-Ilan University [Israël]
Subjects: 010302 applied physics, Instruction stream, business.industry, Computer science, 02 engineering and technology, 01 natural sciences, 020202 computer hardware & architecture, Nonlinear system, Control flow, PACS 85.42, 0103 physical sciences, Basic block, 0202 electrical engineering, electronic engineering, information engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Encoder, Computer hardware
Abstract: International audience; A hardware-based control flow monitoring technique enables to detect both errors in the control flow and the instruction stream being executed on a processor. However, as was shown in recent papers, these techniques fail to detect malicious carefully-tuned manipulation of the instruction stream in a basic block. This paper presents a non-linear encoder and checker that can cope with this weakness.
Published: 2020

25. On-chip reduced-code static linearity test of Vcm -based switching SAR ADCs using an incremental analog-to-digital converter

Author: Renato S. Feitoza, Antonio Gines, Manuel J. Barragan, Salvador Mir, Reliable RF and Mixed-signal Systems (TIMA-RMS), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Instituto de Microelectrónica de Sevilla (IMSE-CNM), Universidad de Sevilla / University of Sevilla-Centro Nacional de Microelectronica [Spain] (CNM)-Consejo Superior de Investigaciones Científicas [Madrid] (CSIC), European Project: 172930120,PENTA,RECHADESTIMD,HADES(2017), Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo, Reliable RF and Mixed-signal Systems (RMS ), and Universidad de Sevilla-Centro Nacional de Microelectronica [Spain] (CNM)-Consejo Superior de Investigaciones Científicas [Madrid] (CSIC)
Subjects: Computer science, 020208 electrical & electronic engineering, Analog-to-digital converter, Successive approximation ADC, Topology (electrical circuits), 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, Converters, 020202 computer hardware & architecture, law.invention, Linearity test, law, PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Code (cryptography), Hardware_INTEGRATEDCIRCUITS, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract: International audience; This paper describes a BIST technique for the static linearity test of $V_{cm}$ -based successive-approximation analog-to-digital converters (SAR ADCs). We discuss the application of reduced-code techniques for the $V_{cm}$ -based SAR ADC topology and present a practical on-chip implementation based on an embedded incremental ADC. Simulation results are provided for validating the feasibility and performance of the proposed on-chip reduced-code static linearity test.
Published: 2020

26. Low Power Tiny Binary Neural Network with improved accuracy in Human Recognition Systems

Author: Frédéric Pétrot, Gian Domenico Licciardo, Luigi Di Benedetto, Antonio De Vita, Alfredo Rubino, Danilo Pau, Università degli Studi di Salerno (UNISA), STMicroelectronics [Agrate Brianza] (ST-AGRATE), System Level Synthesis (SLS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and ANR-19-P3IA-0003,MIAI,MIAI @ Grenoble Alpes(2019)
Subjects: [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], human activity recognition, Computer science, 02 engineering and technology, Accelerometer, Activity recognition, Inertial measurement unit, digital AI acceleration, 0202 electrical engineering, electronic engineering, information engineering, Field-programmable gate array, FPGA, Artificial neural network, business.industry, Deep learning, 020206 networking & telecommunications, Ranging, binarized neural networks, inertial sensors, low power hardware implementation, PACS 85.42, Hardware acceleration, 020201 artificial intelligence & image processing, Artificial intelligence, business, Computer hardware
Abstract: International audience; Human Activity Recognition requires very high accuracy to be effectively employed into practical applications, ranging from elderly care to microsurgical devices. The highest accuracies are achieved by Deep Learning models, but these are not easily deployable in handheld or wearable devices with very constrained resources. We therefore present a new HAR system suitable for a compact FPGA implementation. A new Binarized Neural Network (BNN) architecture achieves the classification based on data from a single tri-axial accelerometer. From our experiments, the effect of gravity and the unknown orientation of the sensor cause a degradation of the accuracy. In order to compensate for these issues, we propose a HW-friendly algorithm to pre-process the raw acceleration signal. Moreover, the very low power and hardware friendly BNN has been trained and validated on the PAMAP2 dataset, for which the pre-processing operations increase the accuracy from 51% to 99% in the best case. A iming for a low-power design, we designed both a custom circuit to perform the pre-processing operations and a hardware accelerator for the BNN. The design on FPGA features a power dissipation of 72 mW and occupies 6788 LUTs.
Published: 2020

27. Latest Trends in Hardware Security and Privacy

Author: Di Natale, G., Regazzoni, F., Albanese, V., Lhermet, F., Loisel, Y., Sensaoui, A., Pagliarini, S., Dilillo, L., Psarakis, M., Siddiqua, T., BEN TITO, Laurence, IEEE, Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Università della Svizzera italiana = University of Italian Switzerland (USI), SiFive France (SiFive France), Tallinn University of Technology (TTÜ), and System and Network Engineering (IVI, FNWI)
Subjects: Hardware security module, business.industry, Computer science, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 05 social sciences, 02 engineering and technology, Computer security, computer.software_genre, Field (computer science), 020202 computer hardware & architecture, Software, 050903 gender studies, PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0509 other social sciences, business, computer
Abstract: International audience; In the last two decades we have witnessed a massive development of technologies (both hardware and software) which have enabled the creation of billions of connected devices. These devices are nowadays used in a very wide range of applications, and they all contain different types of valuable assets, which have been the target of an increasing number of cyber attacks. Both scientific and industrial communities have focused their attention to implement new design processes to reduce the risk of cybersecurity breaches. This paper includes two different contributions in the field of hardware security and privacy
Published: 2020

28. PUF Enrollment and Life Cycle Management: Solutions and Perspectives for the Test Community

Author: Bertrand Cambou, Amir Ali Pour, Naghmeh Karimi, Sylvain Guilley, Vincent Beroulle, Giorgio Di Natale, Jean-Luc Danger, David Hely, BEN TITO, Laurence, IEEE, Département Communications & Electronique (COMELEC), Télécom ParisTech, Secure and Safe Hardware (SSH), Laboratoire Traitement et Communication de l'Information (LTCI), Institut Mines-Télécom [Paris] (IMT)-Télécom Paris-Institut Mines-Télécom [Paris] (IMT)-Télécom Paris, Institut Mines-Télécom [Paris] (IMT)-Télécom Paris, Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Laboratoire de Conception et d'Intégration des Systèmes (LCIS), Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA), Northern Arizona University [Flagstaff], University of Maryland [Baltimore County] (UMBC), and University of Maryland System
Subjects: Stan- dardization, Standardization, Computer science, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 02 engineering and technology, On Line Test, Master key, Enrollment, 0202 electrical engineering, electronic engineering, information engineering, Physically Unclonable Functions (PUF), Challenge/Response Pair Database Management, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS, business.industry, Chip, 020202 computer hardware & architecture, Test (assessment), [SPI.TRON]Engineering Sciences [physics]/Electronics, Identification (information), ComputingMilieux_MANAGEMENTOFCOMPUTINGANDINFORMATIONSYSTEMS, Product life-cycle management, Embedded system, Authentication protocol, PACS 85.42, 020201 artificial intelligence & image processing, business
Abstract: International audience; Physically Unclonable Functions (PUFs) allow to extract unique fingerprints from silicon chips. The applications are numerous: chip identification, chip master key extraction, authentication protocol, unique seeding, etc. However, secure usage of PUF requires some precautions. This paper reviews industrial concerns associated with PUF operation, including those occurring before and after market. Namely, starting from PUF “secure”specifications, aligned with state-of-the-art standards, we explore innovative techniques to handle enrollment and subsequent PUF queries, in nominal as well as in adversarial environment.
Published: 2020

29. Machine learning and hardware security : challenges and opportunities

Author: Naofumi Homma, Amir Ali Pour, Ihab Alshaer, Seetal Potluri, Ville Yli-Mayry, David Hely, Paul D. Franzon, Dirmanto Jap, Aydin Aysu, Priyank Kashyap, Ilia Polian, Elena Ioana Vatajelu, Furkan Aydin, Giorgio Di Natale, Rei Ueno, Vincent Beroulle, Francesco Regazzoni, Shivam Bhasin, Akira Ito, Temasek Laboratories @ NTU, Università della Svizzera italiana = University of Italian Switzerland (USI), Nanyang Technological University [Singapour], Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), North Carolina State University [Raleigh] (NC State), University of North Carolina System (UNC), Laboratoire de Conception et d'Intégration des Systèmes (LCIS), Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA), Tohoku University [Sendai], University of Stuttgart, IEEE, and BEN TITO, Laurence
Subjects: 021110 strategic, defence & security studies, Hardware security module, Post-quantum cryptography, Artificial neural network, business.industry, Computer science, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0211 other engineering and technologies, Cryptography, 02 engineering and technology, Machine learning, computer.software_genre, Public-key cryptography, Machine Learning, Quantum cryptography, PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, Computer science and engineering [Engineering], 020201 artificial intelligence & image processing, Hardware Security, Artificial intelligence, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Digital watermarking, computer
Abstract: International audience; Machine learning techniques have significantly changed our lives. They helped improving our everyday routines, but they also demonstrated to be an extremely helpful tool for more advanced and complex applications. However, the implications of hardware security problems under a massive diffusion of machine learning techniques are still to be completely understood. This paper first highlights novel applications of machine learning for hardware security, such as evaluation of post quantum cryptography hardware and extraction of physically unclonable functions from neural networks. Later, practical model extraction attack based on electromagnetic side- channel measurements are demonstrated followed by a discussion of strategies to protect proprietary models by watermarking them.
Published: 2020

30. IEEE European Test Symposium (ETS)

Author: Elena Ioana Vatajelu, Jaan Raik, Matteo Sonza Reorda, Mehdi B. Tahoori, Maria K. Michael, Artur Jutman, Stephan Eggersgluss, Said Hamdioui, Mentor Graphics Corp. (USA), Computer Engineering - Delft University of Technology (CE), Delft University of Technology (TU Delft), Testonica Labs (Testonica Labs), University of Cyprus [Nicosia], Tallinn Technical University, Politecnico di Torino [Torino] (Polito), Karlsruhe Institute of Technology (KIT), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Politecnico di Torino = Polytechnic of Turin (Polito), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])
Subjects: Engineering, business.industry, 020204 information systems, PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, Library science, 020206 networking & telecommunications, 02 engineering and technology, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, ComputingMilieux_MISCELLANEOUS, Test (assessment)
Abstract: International audience; This paper is dedicated to the IEEE European Test Symposium (ETS). It offers an overview of all the European Test Workshop and Symposium events, from its first edition in 1996 to the next edition in 2020.
Published: 2019

31. Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs

Author: Salvador Mir, Manuel J. Barragan, Renato S. Feitoza, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), European Project: 172930120,PENTA,RECHADESTIMD,HADES(2017), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])
Subjects: Computer science, Capacitive sensing, 020208 electrical & electronic engineering, Linearity, Successive approximation ADC, Topology (electrical circuits), Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, Converters, 020202 computer hardware & architecture, law.invention, Capacitor, Built-in self-test, law, PACS 85.42, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, System on a chip, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract: International audience; This work presents reduced-code strategies for the static linearity test of successive-approximation analog-to-digital converters. Reduced-code techniques for ADC static linearity test may drastically reduce the test time for static linearity characterization. These techniques take advantage of the repetitive operation of SAR ADCs for reducing the number of necessary measurements for static linearity testing. In this paper we discuss the implementation of these techniques for three widely used SAR ADC topologies. Namely, we consider SAR ADCs based on binary-weighted capacitive DACs, split-capacitor DACs and segmented DACs. The proposed techniques are validated by behavioral simulations on three SAR ADC case studies.
Published: 2019

32. Learning-Based Reliability Assessment Method for Detection of Permanent Faults in Clockless Circuits

Author: Ricardo Aquino Guazzelli, Rodrigo Possamai Bastos, Matheus Garay Trindade, Laurent Fesquet, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Circuits, Devices and System Integration (CDSI), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), BEN TITO, Laurence, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)
Subjects: Computer science, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Reliability (computer networking), Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, 01 natural sciences, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Safety, Risk, Reliability and Quality, ComputingMilieux_MISCELLANEOUS, Electronic circuit, 010302 applied physics, Structure (mathematical logic), Resistive touchscreen, 020208 electrical & electronic engineering, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Signature (logic), Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Power (physics), PACS 8542, CMOS, Asynchronous communication, PACS 85.42
Abstract: International audience; Permanent faults are a common issue of contemporary CMOS circuits during fabrication and its lifetime. In order to detect these faults, designers adopt logic and delay-oriented testing approaches to validate the circuit's structure. However, for clockless (i.e. asynchronous) circuits, applying well-known testing approaches is not trivial and bring undesirable overheads. To overcome that, the proposed method in this paper leverages the current signature properties of asynchronous circuits to detect permanent resistive-based faults. Through simulation experiments, we show the natural ability of asynchronous circuits in providing useful current signatures for identifying the presence of resistive-based faults. Moreover, the results demonstrate that our testing technique requires no extra circuitry or power ports to detect resistive-short faults = 70k Omega.
Published: 2019

33. Feature selection and feature design for machine learning indirect test: a tutorial review

Author: Manuel J. Barragan, Gildas Leger, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Instituto de Microelectrónica de Sevilla (IMSE-CNM), Universidad de Sevilla-Centro Nacional de Microelectronica [Spain] (CNM)-Consejo Superior de Investigaciones Científicas [Madrid] (CSIC), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Instituto de Microelectrónica de Sevilla (IMSE-CNM CSIC), and Centro Nacional de Microelectronica [Spain] (CNM)-Consejo Superior de Investigaciones Científicas [Spain] (CSIC)
Subjects: Computer science, Circuit performance, business.industry, 020208 electrical & electronic engineering, Feature selection, 02 engineering and technology, Machine learning, computer.software_genre, 020202 computer hardware & architecture, Feature design, Set (abstract data type), Key point, Indirect test, PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, Artificial intelligence, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, computer, ComputingMilieux_MISCELLANEOUS
Abstract: International audience; Machine learning indirect test replaces costly specification measurements by simpler signatures and use modern learning algorithms to map these signatures to specifications. Defining a set of relevant signatures that appropriately captures the circuit performance degradation mechanisms is then a key point for enabling machine learning indirect test. In this tutorial we review some methodologies for selecting and designing such a set of information rich signatures.
Published: 2019

34. Efficient generation of data sets for one-shot statistical calibration of RF/mm-wave circuits

Author: Estelle Lauga-Larroze, Salvador Mir, Gildas Leger, Manuel J. Barragan, Florent Cilici, Sylvain Bourdcl, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Instituto de Microelectrónica de Sevilla (IMSE-CNM), Universidad de Sevilla-Centro Nacional de Microelectronica [Spain] (CNM)-Consejo Superior de Investigaciones Científicas [Madrid] (CSIC), Laboratoire de Radio-Fréquence et d'Intégration de Circuits (RFIC-Lab), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), European Project: 737454,H2020,H2020-ECSEL-2016-1-RIA-two-stage,TARANTO(2017), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Instituto de Microelectrónica de Sevilla (IMSE-CNM CSIC), Centro Nacional de Microelectronica [Spain] (CNM)-Consejo Superior de Investigaciones Científicas [Spain] (CSIC), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Université Grenoble Alpes (UGA), European Project: 737454,TARANTO, and Universidad de Sevilla / University of Sevilla-Centro Nacional de Microelectronica [Spain] (CNM)-Consejo Superior de Investigaciones Científicas [Madrid] (CSIC)
Subjects: Computer science, Calibration (statistics), 020208 electrical & electronic engineering, Process (computing), Regression analysis, 02 engineering and technology, 020202 computer hardware & architecture, Data set, Set (abstract data type), Variable (computer science), Simple (abstract algebra), PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS, Electronic circuit
Abstract: International audience; Millimeter-wave circuits in current nanometric technologies are especially sensitive to process variations, which can seriously degrade the device behavior and reduce fabrication yield. To tackle this issue, conservative designs and large design margins are widely used solutions. Another approach consists in introducing variable elements, also called tuning knobs, to allow post-fabrication tuning. One-shot statistical calibration techniques take advantage of advanced machine learning regression tools to propose a set of tuning knobs values that enhance the circuit performance based on simple measurements. Training the regression models require a huge amount of data covering the device performances, the effect of the tuning knobs and the simple measurements that guide the regression. In this work, we propose an efficient method for generating such a data set that reduces noticeably the size of the required training set for an accurate calibration.
Published: 2019

35. HATE: a HArdware Trojan Emulation Environment for Microprocessor-based Systems

Author: Luca Cassano, Andrea Zanetti, Cristiana Bolchini, Giorgio Di Natale, Giampiero Repole, Ivan Montalbano, Politecnico di Milano [Milan] (POLIMI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)
Subjects: Hardware security module, Emulation, Computer science, business.industry, Supply chain, 0211 other engineering and technologies, 02 engineering and technology, Benchmarking, 020202 computer hardware & architecture, law.invention, Set (abstract data type), Microprocessor, Software, law, Hardware Trojan, Embedded system, PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, ComputingMilieux_MISCELLANEOUS, 021106 design practice & management
Abstract: The constant quest of low production cost and short time-to-market, together with the growing complexity of integrated circuits led to the globalization of the supply chain of silicon devices. One of the threats related to such a supply chain are Hardware Trojan Horses (HWTs), that, in the last years, became a serious issue not only for academy but also for industry. Although a large number of methodologies for HWTs prevention, detection and tolerance have been proposed, there is a lack of well-recognized methods and metrics to evaluate their effectiveness. In this paper we present HATE 1, a HArdware Trojan Emulation Environment. The goal of HATE is twofold: (i) the tool can be used to analyse whether a given HWT (or a given set of HWTs) is activated by a software running on a microprocessor, and (ii) it can be used to assess HWTs detection techniques in microprocessors against a set of generated HWTs (either randomly or not). HATE represents, in our vision, a step towards the definition of a reference benchmarking scenario, to provide a comparative ground for evaluating different proposals focusing on HWT detection/tolerance. A subset of MiBench programs have been used to analyse the efficiency of HATE.1HATE is freely available at http://cassano.faculty.polimi.it/
Published: 2019

36. Alternatives to Fault Injections for Early Safety/Security Evaluations

Author: Giorgio Di Natale, Michele Portolan, Regis Leveugle, Stefano Di Carlo, Alberto Bosio, Alessandro Savino, BEN TITO, Laurence, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Politecnico di Torino = Polytechnic of Turin (Polito), École Centrale de Lyon (ECL), Université de Lyon, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), and Politecnico di Torino [Torino] (Polito)
Subjects: [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], Computer science, Fault Injection, 02 engineering and technology, Certification, Functional Safety, Fault (power engineering), Software, 0202 electrical engineering, electronic engineering, information engineering, Dependability, ComputingMilieux_MISCELLANEOUS, Functional safety, business.industry, Cyber-physical system, DIGITAL SYSTEM DESIGN TEST AND VERIFICATION, 020207 software engineering, Fault injection, Reliability, 020202 computer hardware & architecture, Reliability engineering, Cost reduction, PACS 85.42, dependability analysis, business
Abstract: Functional Safety standards like ISO 26262 require a detailed analysis of the dependability of components subjected to perturbations. Radiation testing or even much more abstract RTL fault injection campaigns are costly and complex to set up especially for SoCs and Cyber Physical Systems (CPSs) comprising intertwined hardware and software. Moreover, some approaches are only applicable at the very end of the development cycle, making potential iterations difficult when market pressure and cost reduction are paramount. In this tutorial, we present a summary of classical state-of-the-art approaches, then alternative approaches for the dependability analysis that can give an early yet accurate estimation of the safety or security characteristics of HW-SW systems. Designers can rely on these tools to identify issues in their design to be addressed by protection mechanisms, ensuring that system dependability constraints are met with limited risk when subjected later to usual fault injections and to e.g., radiation testing or laser attacks for certification.
Published: 2019

37. Providing Confidentiality and Integrity in Ultra Low Power IoT Devices

Author: Emanuele Valea, Mathieu Da Silva, Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)
Subjects: Hardware security module, IoT, Computer science, Encryption, Context (language use), 02 engineering and technology, 0202 electrical engineering, electronic engineering, information engineering, Hardware Security, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, PUF, Implementation, business.industry, Ciphers, Context Saving, Nonvolatile memory, Context, 020206 networking & telecommunications, Random access memory, Power supplies, 020202 computer hardware & architecture, Non-volatile memory, Embedded system, PACS 85.42, Central processing unit, State (computer science), business, Energy harvesting
Abstract: International audience; IoT devices for low power applications often rely on energy harvesting techniques. In these implementations, IoT nodes must be aware of the amount of available energy. When the energy is about to run out, they need to halt and save the context of the CPU, which is restored as soon as the energy is available again. Some of the existing techniques rely on the transfer of the scan chains content to a Non-Volatile Memory (NVM). However, the saved state of the device might be the target of malicious attacks, including tampering and theft of confidential data. One solution is to provide the encryption and the integrity of context data. In this paper, we propose the implementation of an additional module interposed between the CPU and the NVM, which provides both these security features.
Published: 2019

38. Approximate computing design exploration through data lifetime metrics

Author: Michele Portolan, Stefano Di Carlo, Regis Leveugle, Alessandro Savino, Politecnico di Torino = Polytechnic of Turin (Polito), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Politecnico di Torino [Torino] (Polito), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), and BEN TITO, Laurence
Subjects: [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], Global system, Mathematical optimization, Approximate computing, Exploit, Design space exploration, Computer science, DIGITAL SYSTEM DESIGN TEST AND VERIFICATION, 02 engineering and technology, Design Space Exploration, 020202 computer hardware & architecture, Error metrics, PACS 85.42, 020204 information systems, Design exploration, 0202 electrical engineering, electronic engineering, information engineering, Approximate Computing, design-space-exploration
Abstract: International audience; When designing an approximate computing system, the selection of the resources to modify is key. It is important that the error introduced in the system remains reasonable, but the size of the design exploration space can make this extremely difficult. In this paper, we propose to exploit a new metric for this selection: data lifetime. The concept comes from the field of reliability, where it can guide selective hardening: the more often a resource handles "live" data, the more critical it becomes, the more important it will be to protect it. In this paper, we propose to use this same metric in a new way: identify the less critical resources as approximation targets in order to minimize the impact on the global system behavior and therefore decrease the impact of approximation while increasing gains on other criteria.
Published: 2019

39. AlN-on-Si Square Diaphragm Piezoelectric Micromachined Ultrasonic Transducer with Extended Range of Detection

Author: Suresh Alasatri, Joshua E.-Y. Lee, Libor Rufer, City University of Hong Kong [Hong Kong] (CUHK), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), BEN TITO, Laurence, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)
Subjects: touchless, Materials science, Silicon, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, chemistry.chemical_element, lcsh:A, Nitride, 01 natural sciences, aluminum nitride (AlN), Printed circuit board, 0103 physical sciences, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010301 acoustics, 010302 applied physics, Microelectromechanical systems, business.industry, Diaphragm (acoustics), piezoelectric micromachined ultrasonic transducer (pMUT), Chip, Piezoelectricity, chemistry, aluminum, PACS 85.42, Optoelectronics, Ultrasonic sensor, piezoelectric, lcsh:General Works, business, touchless sensing
Abstract: International audience; We present aluminum nitride (AlN) on silicon (Si) CMOS-compatible piezoelectric micromachined ultrasonic transducers (pMUTs) with an extended detection range of up to 140cm for touchless sensing applications. The reported performance surpasses the current state-of-art for AlN-based pMUTs in terms of the maximum range of detection using just a pair of pMUTs (as opposed to an array of pMUTs). The extended range of detection has been realized by using a larger diaphragm allowed by fabricating a thicker diaphragm than most other pMUTs reported to date. Using a pair of pMUTs, we experimentally demonstrate the capability of range-finding by correlating the time-of-flight (TOF) between the transmit (TX) and receive (RX) pulse. The results are obtained on an experimental setup where the MEMS chip is interconnected with a customized printed circuit board (PCB) using Al wire bonds.
Published: 2018

40. Laser fault injection at the CMOS 28 nm technology node: an analysis of the fault model

Author: Regis Leveugle, Vincent Beroulle, Louis-Barthelemy Faber, Paolo Maistri, Giorgio Di Natale, Marie-Lise Flottes, Stephan De Castro, Bruno Rouzeyre, David Hely, Philippe Gendrier, Philippe Candelier, Athanasios Papadimitriou, Jean-Max Dutertre, Département Systèmes et Architectures Sécurisés (SAS-ENSMSE), École des Mines de Saint-Étienne (Mines Saint-Étienne MSE), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-CMP-GC, Institut Mines-Télécom [Paris] (IMT), Laboratoire de Conception et d'Intégration des Systèmes (LCIS), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Université Grenoble Alpes (UGA), STMicroelectronics [Crolles] (ST-CROLLES), TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])
Subjects: 010302 applied physics, 010308 nuclear & particles physics, Computer science, Transistor, Laser fault injection, Integrated circuit, Fault injection, Hardware_PERFORMANCEANDRELIABILITY, Fault (power engineering), 01 natural sciences, law.invention, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], CMOS, Hardware security, law, PACS 85.42, 0103 physical sciences, Electronic engineering, Node (circuits), Fault model, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Electronic circuit
Abstract: International audience; S. Skorobogatov and R. Anderson identified laser illumination as an effective technique to conduct fault attacks in 2002. In these early days of laser-induced fault injection, it was proven to be possible to inject single-bit faults into integrated circuits. This corresponds to the more restrictive fault model found in the fault attack bibliography. The target area under laser illumination (a few micrometers, down to ∼ 1 μm) broadly matched that of a single transistor. It was consistent with a single- bit fault model. However, since then the technology of secure devices has evolved. In current circuits even the smallest laser spots may illuminate several logic cells. This raises the question of the validity of the single-bit fault model: does it still hold? In this work, we report an assessment of its validity through experimental results obtained from circuits designed at the 28 nm CMOS technology node. We also describe the main properties of the corresponding fault model obtained from both static and dynamic experiments.
Published: 2018

41. The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks

Author: Bruno Rouzeyre, Athanasios Papadimitriou, Vincent Beroulle, Jean-Max Dutertre, David Hely, Marie-Lise Flottes, Louis-Barthelemy Faber, Regis Leveugle, Paolo Maistri, Philippe Gendrier, Philippe Candelier, Giorgio Di Natale, Département Systèmes et Architectures Sécurisés (SAS-ENSMSE), École des Mines de Saint-Étienne (Mines Saint-Étienne MSE), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-CMP-GC, Institut Mines-Télécom [Paris] (IMT), Laboratoire de Conception et d'Intégration des Systèmes (LCIS), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics [Crolles] (ST-CROLLES), TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Université Grenoble Alpes (UGA), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)
Subjects: Materials science, Laser, Silicon on insulator, Hardware_PERFORMANCEANDRELIABILITY, Integrated circuit, CMOS bulk, 01 natural sciences, law.invention, Semiconductor laser theory, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], law, Fault injection, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010302 applied physics, 010308 nuclear & particles physics, business.industry, Transistor, CMOS, PACS 85.42, Index Terms-Laser fault injection, Optoelectronics, FD-SOI, Node (circuits), business
Abstract: International audience; At first used to emulate the effects of radioactive ionizing particules passing through integrated circuits (ICs), laser illumination is also used to inject faults into the computations of secure ICs for the purpose of retrieving secret data. The CMOS FD-SOI technology is expected to be less sensitive to laser faults injection than the more usual CMOS bulk technology. We report in this work an experimental assessment of the interest of using FD-SOI rather than CMOS bulk to decrease laser sensitivity. Our experiments were conducted on test chips at the 28 nm node for both technologies with laser pulse durations in the picosecond and nanosecond ranges.
Published: 2018

42. An FPGA target for the StarPU heterogeneous runtime system

Author: Olivier Muller, François Broquedis, Georgios Christodoulis, Manuel Selva, Frédéric Desprez, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Compiler Optimization and Run-time Systems (CORSE), Inria Grenoble - Rhône-Alpes, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-Laboratoire d'Informatique de Grenoble (LIG ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), ANR-11-LABX-0025,PERSYVAL-lab,Systemes et Algorithmes Pervasifs au confluent des mondes physique et numérique(2011), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-Laboratoire d'Informatique de Grenoble (LIG), Université Pierre Mendès France - Grenoble 2 (UPMF)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Université Pierre Mendès France - Grenoble 2 (UPMF)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), and ANR-11-LABX-0025-01,PERSYVAL-lab,Systèmes et Algorithmes Pervasifs au confluent des mondes physique et numérique(2011)
Subjects: [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], Runtime system, Task (computing), Computer architecture, Computer science, PACS 85.42, Task analysis, Code (cryptography), Energy consumption, Field-programmable gate array, FPGA, Blocking (computing), Matrix multiplication
Abstract: International audience; Heterogeneity in HPC nodes appears as a promising solution to improve the execution of a wide range of scientific applications, regarding both performance and energy consumption. Unlike CPUs and GPUs, FPGAs can be configured to fit the application needs, making them an appealing target to extend traditional heterogeneous HPC architectures. However, exploiting them requires an in-depth knowledge of low-level hardware and high expertise on vendor-provided tools, which should not be the primary concern of HPC application programmers. In this paper, we present the first results of the HEAVEN project that aims at designing a framework enabling a more straightforward development of scientific applications over FPGA enhanced platforms. Our work is concentrated on providing a framework, which will require the minimum knowledge of the underlying architecture, as well as fewer changes to the existing code. To fulfill these requirements, we extend the StarPU task programming library that initially targets heterogeneous architectures to support FPGA. We use Vivado HLS, a high-level synthesis tool to deliver efficient hardware implementations of the tasks from high-level languages like C/C++. For the evaluation of our proposal, we present code snippets for a blocking version of matrix multiplication, illustrating the ease of development our approach delivers. We also show preliminary results regarding the performance of the FPGA version, which validate our proof-of-concept implementation.
Published: 2018

43. Mixed-signal test automation: are we there yet?

Author: Manuel J. Barragan, Gildas Leger, Instituto de Microelectrónica de Sevilla (IMSE-CNM), Universidad de Sevilla-Centro Nacional de Microelectronica [Spain] (CNM)-Consejo Superior de Investigaciones Científicas [Madrid] (CSIC), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Instituto de Microelectrónica de Sevilla (IMSE-CNM CSIC), Centro Nacional de Microelectronica [Spain] (CNM)-Consejo Superior de Investigaciones Científicas [Spain] (CSIC), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)
Subjects: Computer science, business.industry, 020208 electrical & electronic engineering, Mixed-signal integrated circuit, 02 engineering and technology, Design knowledge, Automation, 020202 computer hardware & architecture, Test (assessment), Domain (software engineering), Embedded system, PACS 85.42, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Device under test, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Electronic circuit
Abstract: International audience; Testing analog, mixed-signal and RF (AMS-RF) cir- cuits represents a significant cost component for testing complex SoCs. Moreover, AMS-RF test generation and validation are still largely handcrafted tasks that rely on expert design knowledge for each particular Device Under Test (DUT). Mixed-signal test automation has been sought by the test community for the last decades, trying to mimic the success of digital test approaches. Indeed, in the digital domain, test is vastly automated and standard techniques are already available (ATPGs, BIST, scan registers, etc.). In the last decade, a methodology based on leveraging the power of machine learning algorithms has been proposed for AMS-RF circuits that opens the door to a higher level of automation. In this paper we review recent results in this line and try to put together what could be such a complete methodology and what remains to be done.
Published: 2018

44. Thermal Stability of Micro-Structured PDMS Piezo-Electrets under Various Polymeric Reticulation Ratios for Sensor Applications

Author: Alain Sylvestre, Achraf Kachroudi, Skandar Basrour, Laboratoire de Génie Electrique de Grenoble (G2ELab), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Département de pharmacochimie moléculaire (DPM ), Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Institut Polytechnique de Grenoble - Grenoble Institute of Technology-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Garcia, Sylvie
Subjects: Materials science, Piezoelectric coefficient, piezo-electret, Modulus, lcsh:A, 02 engineering and technology, 7. Clean energy, Energy harvester, thermal stability, 0203 mechanical engineering, PDMS, Thermally stimulated discharge, Thermal stability, Composite material, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Prepolymer, ComputingMilieux_MISCELLANEOUS, electro-active polymer, piezoelectricity, [SPI.NRJ]Engineering Sciences [physics]/Electric power, 021001 nanoscience & nanotechnology, Piezoelectricity, 020303 mechanical engineering & transports, PACS 85.42, Electret, lcsh:General Works, 0210 nano-technology, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract: The effect of the polymeric reticulation on the thermal stability of the piezoelectricity of a micro-structured PDMS piezo-electret was investigated. This new family of flexible piezoelectric materials with very low Young’s modulus is used for wearable sensors and energy harvester devices. The best thermal stability was obtained for the piezo-electret material made from the ratio 1:10 between the prepolymer and the crosslinking agent with a longitudinal piezoelectric coefficient d33 = 350 pC/N. The highest piezoelectric coefficient d33 = 750 pC/N was obtained for the ratio 1:20, but the piezoelectricity was lost at 45 °C by thermally stimulated discharge
Published: 2017

45. Role of Laser-Induced IR Drops in the Occurrence of Faults: Assessment and Simulation

Author: Jean-Max Dutertre, Rodrigo Possamai Bastos, Raphael A. C. Viera, Philippe Maurine, Smart Integrated Electronic Systems (SmartIES), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Département Systèmes et Architectures Sécurisés (SAS-ENSMSE), École des Mines de Saint-Étienne (Mines Saint-Étienne MSE), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-CMP-GC, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)
Subjects: Computer science, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, CMOS Transistors, Hardware security, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Soft error, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Power network design, Electronic circuit, 010302 applied physics, Ir-drop, business.industry, Laser fault injection, Circuit faults, Fault injection, 020202 computer hardware & architecture, Stuck-at fault, CMOS, Integrated circuit modeling, Embedded system, Logic gate, PACS 85.42, Transient (oscillation), business
Abstract: International audience; Laser fault injection attacks induce transient faults into ICs by locally generating transient currents capable of temporarily flipping the outputs of logic gates. Laser fault injection may be anticipated or studied by using simulation tools at different abstraction levels: physical, electrical or logical. At the electrical level, the general laser-fault injection model is based on the addition of current sources to the various sensitive nodes of CMOS transistors. This type of electrical model does not take into account the large transient current components also induced between VDD and GND as a result of laser illumination. Such current components have no direct effect on the logic gate output nodes. Still, they provoke a significant IR-drop that may, in turn, contribute to the fault injection process. This paper describes our research on the assessment of this contribution. It introduces an upgraded electrical model taking the laser-induced IR-drop into account. It also proposes a methodology that allows the model's use to simulate laser-induced faults at electrical level in large-scale circuits. On the basis of simulations with a case-study circuit, we found that, depending on the parameters of the laser pulse, the number of injected faults may be underestimated by a factor as large as 48 if the laser-induced IR-drop is ignored. This may lead to incorrect estimations of the fault injection threshold, which is especially relevant for the design of countermeasure techniques for secure integrated systems.
Published: 2017

46. Ternary neural networks for resource-efficient AI applications

Author: Frédéric Pétrot, Vincent Leroy, Hande Alemdar, Adrien Prost-Boucle, Laboratoire d'Informatique de Grenoble (LIG ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), ScaLable Information Discovery and Exploitation [Saint Martin d’Hères] (SLIDE), Laboratoire d'Informatique de Grenoble (LIG), Université Pierre Mendès France - Grenoble 2 (UPMF)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Université Pierre Mendès France - Grenoble 2 (UPMF)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Université Pierre Mendès France - Grenoble 2 (UPMF)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), ScaLable Information Discovery and Exploitation [Grenoble] (SLIDE), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])
Subjects: FOS: Computer and information sciences, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], Computer Science - Artificial Intelligence, Computer science, 02 engineering and technology, Machine Learning (cs.LG), [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], 0202 electrical engineering, electronic engineering, information engineering, Neural and Evolutionary Computing (cs.NE), Dropout (neural networks), ComputingMilieux_MISCELLANEOUS, Hardware architecture, Artificial neural network, business.industry, Deep learning, 020208 electrical & electronic engineering, Computer Science - Neural and Evolutionary Computing, 020202 computer hardware & architecture, Computer Science - Learning, Artificial Intelligence (cs.AI), Computer engineering, PACS 85.42, Benchmark (computing), Applications of artificial intelligence, Artificial intelligence, Ternary operation, business
Abstract: International audience; —The computation and storage requirements for Deep Neural Networks (DNNs) are usually high. This issue limits their deployability on ubiquitous computing devices such as smart phones, wearables and autonomous drones. In this paper, we propose ternary neural networks (TNNs) in order to make deep learning more resource-efficient. We train these TNNs using a teacher-student approach based on a novel, layer-wise greedy methodology. Thanks to our two-stage training procedure, the teacher network is still able to use state-of-the-art methods such as dropout and batch normalization to increase accuracy and reduce training time. Using only ternary weights and activations, the student ternary network learns to mimic the behavior of its teacher network without using any multiplication. Unlike its {-1,1} binary counterparts, a ternary neural network inherently prunes the smaller weights by setting them to zero during training. This makes them sparser and thus more energy-efficient. We design a purpose-built hardware architecture for TNNs and implement it on FPGA and ASIC. We evaluate TNNs on several benchmark datasets and demonstrate up to 3.1× better energy efficiency with respect to the state of the art while also improving accuracy.
Published: 2017

47. Modeling of structural-fluidic interactions for the design of digital MEMS speakers in hearing aids

Author: G. De Pasquale, Skandar Basrour, V. Pedio, Libor Rufer, Aurelio Soma, Politecnico di Torino [Torino] (Polito), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés [2016-2019] (TIMA [2016-2019]), Institut polytechnique de Grenoble - Grenoble Institute of Technology [2007-2019] (Grenoble INP [2007-2019])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), BEN TITO, Laurence, Politecnico di Torino = Polytechnic of Turin (Polito), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])
Subjects: Engineering, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Acoustics, Microfluidics, microfluidics, 02 engineering and technology, 01 natural sciences, Field (computer science), Reliability (semiconductor), Hardware_GENERAL, 0103 physical sciences, smart systems, Electronic engineering, digital speakers, Fluidics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Bio-MEMS, hearing aids, FEM modeling, Sound wave, Microelectromechanical systems, Functional specification, Smart system, 010308 nuclear & particles physics, business.industry, 021001 nanoscience & nanotechnology, PACS 85.42, 0210 nano-technology, business
Abstract: International audience; Micro Electro-Mechanical Systems (MEMS), applied to the field of hearing aids, offer ample possibilities for improving of performance, reliability and functional specifications, and they are also promising in terms of energy saving. In this paper, some of the major design problems relating to the use of MEMS for sound waves generation inside the ear canal are analyzed.
Published: 2017

48. Memristive devices: Technology, design automation and computing frontiers

Author: Hoang Anh Du Nguyen, Mario Barbareschi, Elena Ioana Vatajelu, Said Hamdioui, Alberto Bosio, Marcello Traiola, Barbareschi, M., Bosio, A., Du Nguyen, H. A., Hamdioui, S., Traiola, M., Vatajelu, E. I., Università degli studi di Napoli Federico II, TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Computer Engineering - Delft University of Technology (CE), Delft University of Technology (TU Delft), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])
Subjects: Component, Emerging technologies, Computer science, 02 engineering and technology, Memristor, CAD tool, 01 natural sciences, law.invention, memory, law, Memo, Architecture, 0103 physical sciences, Electronic engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, computer architecture, Massively parallel, Design technology, 010302 applied physics, Hardware_MEMORYSTRUCTURES, emerging technologie, Reconfigurability, 021001 nanoscience & nanotechnology, Logic synthesis, Memistor, Computer architecture, PACS 85.42, logic synthesi, 0210 nano-technology, Efficient energy use
Abstract: International audience; The memristor is an emerging technology which is triggering intense interdisciplinary activity. It has the potential of providing many benefits, such as energy efficiency, density, reconfigurability, nonvolatile memory, novel computational structures and approaches, massive parallelism, etc. These characteristics may lead to deeply revise existing computing and storage paradigms. This paper presents a comprehensive overview of memristor technology and its potential to design a new computational paradigm.
Published: 2017

49. Assignment of Vertical-Links to Routers in Vertically-Partially-Connected 3-D-NoCs

Author: Sahar Foroutan, Abbas Sheibanyrad, Frédéric Pétrot, Architecture et Logiciels pour Systèmes Embarqués sur Puce (ALSOC), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés [2007-2015] (TIMA [2007-2015]), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology [2007-2019] (Grenoble INP [2007-2019])-Centre National de la Recherche Scientifique (CNRS)
Subjects: Engineering, Optimization problem, Elevator, business.industry, Dimension (graph theory), Topology (electrical circuits), Network topology, Computer Graphics and Computer-Aided Design, PACS 85.42, Hardware_INTEGRATEDCIRCUITS, [INFO]Computer Science [cs], Network performance, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Electrical and Electronic Engineering, Wormhole, Network performance degradation, business, Software, Computer network
Abstract: International audience; Assignment of Vertical-Links to Routers in Vertically-Partially-Connected 3-D-NoCsType : Article dans des revues avec comité de lectureAbstract : This paper addresses elevator assignment in vertically-partially-connected 3-D-networks-on-chip (NoCs). Elevators are vertical links between dies. Because of yield issues, Through-Silicon-Via (TSV) cost, and heterogeneity in dimension, topology, and technology of different dies, vertically-partially-connected topologies seem unavoidable in the emerging 3-D-NoCs as opposed to fully-connected topologies. In such partially-connected topologies, as there are fewer elevators than routers, the assignment of elevators to routers becomes a new 3-D-specific optimization problem. An improper assignment can lead to dramatic network performance degradation. This paper proposes an elevator assignment method for best-effort wormhole 3-D-NoCs to improve the average network performance. Experimental results show an improvement of about 90% even compared to a greedy (intrinsically good) initial assignment.
Published: 2014

50. ADC techniques for optimized conversion time in CMOS image sensors

Author: C. Tubert, P. Mellot, Salvador Mir, C. Pastorelli, STMicroelectronics [Crolles] (ST-CROLLES), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Torella, Lucie, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])
Subjects: CMOS, Computer science, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, PACS 85.42, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, Hardware_PERFORMANCEANDRELIABILITY, Image sensor, Hardware_ARITHMETICANDLOGICSTRUCTURES, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION
Abstract: International audience; For several decades, many CMOS Image Sensors (CIS) with a small pixel size have used single slope column parallel ADCs (SS-ADC). It is well known that the main drawback of this ADC is the conversion speed. This paper presents several ADC architectures which improve the speed of a SS-ADC. Different architectures are compared in terms of ADC resolution, power consumption, noise and conversion time.
Published: 2016

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