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We propose an analog front-end integrated circuit (IC) design for a readout IC (ROIC), which applies a fixed-voltage-bias sensing method with a capacitance transimpedance amplifier (CTIA) to an input stage in order to simplify the circuit structure of the ROIC and the IR sensor characteristic control. For a sample-and-hold stage, in order to display and control a signal detected by the IR sensor using a 2-D focal plane array, a differential delta sampling circuit is proposed, which effectively removes the fixed pattern noise. In addition, a two-stage variable-gain amplifier equipped with a rail-to-rail fully differential operational amplifier is applied to the ROIC to achieve high voltage sensitivity. The output characteristic of the proposed device is 30.84 mV/K and the linearity error rate is less than 0.07%. After checking the performance of the ROIC using an HSPICE simulation, the chip is manufactured and measured using the United Microelectronics Corporation Japan 0.35- $\mu\mbox{m}$ standard CMOS process to confirm that the simulation results from the actual design are in close agreement with the measurement results.

Super junction trench gate power MOSFETs have been receiving attention in terms of the trade-off between breakdown voltage and on-resistance [1]. The vertical structure of super junction trench gate power MOSFETs allows the on-resistance to be reduced compared with conventional Trench Gate Power MOSFETs. The heat release of devices is also decreased with the reduction of on-resistance. In this paper, Lattice Temperature of two devices, Trench Gate Power MOSFET and Super junction trench gate power MOSFET, are compared in several temperature circumstance with the same Breakdown Voltage and Cell-pitch. The devices were designed by 100V Breakdown voltage and measured from 250K Lattice Temperature. We have tried to investigate how much temperature rise in the same condition. According as temperature gap between top of devices and bottom of devices, Super junction trench gate power MOSFET has a tendency to generate lower heat release than Trench Gate Power MOSFET. This means that Super junction trench gate power MOSFET is superior for wide-temperature range operation. When trench etching process is applied for making P-pillar region, trench angle factor is also important component. Depending on trench angle, characteristics of Super junction device are changed. In this paper, we focus temperature characteristic as changing trench angle factor. Consequently, Trench angle factor don’t have a great effect on temperature change.

In Super Junction (SJ) MOSFETs, charge balance is the most important issue of the SJ fabrication process. In order to achieve the best electrical characteristics, such as breakdown voltage and on-resistance, the N-type and P-type drift regions must be fully depleted when the drain bias approaches the breakdown voltage, which is known as the charge balance condition. In conventional charge balance analysis, based on multi-epi process SJ MOSFETs, analytical model has only N, P pillar width and doping concentration parameter. But applying a conventional charge balance principle to trench filling process, easier than Multi-epi process, is impossible due to the missing of the trench angle parameter. To achieve much more superior characteristics of on-resistance in trench filling SJ MOFET, the appropriate trench angle is necessary. So in this paper, modulated charge balance analysis is proposed, in which a trench angle parameter is added. The proposed method is validated using the TCAD simulation tool.

Insulated Gate Bipolar Transistors(IGBTs) have received wide attention because of their high current conduction and good switching characteristics. To reduce the power loss of IGBT, the onstate voltage drop should be lowered and the switching time should be shortened. However, there is trade-off between the breakdown voltage and the on-state voltage drop. The FLoatingIsland(FLI) structure can lower the on-state voltage drop without reducing breakdown voltage. In this paper, The FLI IGBT shows an on-state voltage drop that is 22.5% lower than the conventional IGBT, even though the breakdown voltages of each IGBT are almost identical.

In this paper, fabricated by MEMS uncooled micro-bolometer detector for the study in the infrared sensitivity enhancement. Absorption layer SiOx-Metal series MDTF (metal-dielectric thin film) by high absorption rate and has a high thermal coefficient of resistance, low noise characteristics were implemented. Then MDTF were made in a vacuum deposition method. And MDTF for the analysis of the physical properties of silicon wafers were fabricated, TCR (temperature coefficient of resistance) value was made in order to measure the glass wafer and FT-IR (Fourier Transform Infrared spectroscopy) values were made in order to measure the germanium window. The analyzed results of MDTF -3 [%/K] has more characteristics of the TCR. And 8~12 um wavelength region close to 70% in the absorption characteristic.

Protected Circuit Module protects battery from over-charge and over-discharge, also prevents accidental explosion. Therefore, power MOSFET is essential to operate as a switch within the module. To reduce power loss of MOSFET, the on state voltage drop should be lowered and the switching time should be shorted. However there is trade-off between the breakdown voltage and the on state voltage drop. The TDMOS can reduce the on state voltage drop. In this paper, effect of design parameter variation on electrical properties of TDMOS, were analyzed by computer simulation. According to the analyzed results, the optimization was performed to get 65% higher breakdown voltage and 17.4% on resistance enhancement.

IGBT (insulated gate bipolar transistor) have received wide attention because of their high current conduction and good switching characteristics. To reduce the power loss of IGBT, the on state voltage drop should be lowered and the switching time should be shorted. However, there is Trade-off between the breakdown voltage and the on state voltage drop. To achieving good electrical characteristics, field stop IGBT (FS IGBT) is proposed. In this paper, 1,200 V planar gate non punch-through IGBT (planar gate NPT IGBT), planar gate FS IGBT and trench gate FS IGBT is designed and optimized. The simulation results are compared with each three structures. In results, we optain optimal design parameters and confirm excellence of trench gate FS IGBT. Experimental result by using medici, shows 40% improvement of on state voltage drop.

Department of Electrical Engineering, Korea University, Seoul 136-701, Korea(Received March 16, 2012; Revised March 21, 2012; Accepted March 22, 2012)Abstract: IGBT (insulated gate bipolar transistor) has been widely used around the power industry as it has good switching performance and its excellent conductance. In order to reduce power loss during switch turn-on state, it is essential to reduce its resistance. However, trade off relationship between breakdown voltage and device conductance is the greatest obstacle on the way of improvement. Floating island structure is one of the solutions. Still, under optimized device condition for the best performance, improvement rate is negligible. Therefore, this paper suggests adding trench gate on floating island structure to eliminate JFET (junction field effect transistor) area to reduce resistance and activate floating island effect. Experimental result by 2D simulation using TCAD, shows 20% improvement of turn-on state voltage drop.Keywords: Floating island, Trench gate, IGBT, Power semiconductor device

We propose a Readout Integrated Circuit (ROIC), which applies a fixed current bias sensing method to the input stage in order to simplify the circuit structure and the infrared sensor characteristic control. For the sample-and-hold stage to display and control a signal detected by the infrared sensor using a two-dimensional (2D) focal plane array, a differential delta sampling (DDS) circuit is proposed, which effectively removes the FPN. In addition, the output characteristic is improved to have wider bandwidth and higher gain by applying a two-stage variable gain amplifier (VGA). The output characteristic of the proposed device was 23.91 ㎷/℃, and the linearity error rate was less than 0.22%. After checking the performance of the ROIC using HSPICE simulation, the chip was manufactured and measured using the SMIC 0.35 ㎛ standard CMOS process to confirm that the simulation results from the actual design are in good agreement with the measurement results.

A uncooled infrared ray sensor used in an infrared thermal imaging detector has many advantages. But because the uncooled infrared ray sensor is made by MEMS (micro-electro-mechanical system) process variation of offset is large. In this paper, to solve process variation of offset a ROIC for uncooled infrared ray sensor that has process variation of offset compensation technique using differential delta sampling and reference signal compensation circuit was proposed. As a result of simulation that uses the proposed ROIC, it was possible to acquire compensated output characteristics without process variation of offsets.

Three-dimensional (3D) dynamic random-access memory (DRAM) with TSVs has been proposed due to continuous demands for low-power and high-density memory without IO loading limitation. However, the process difference among the stacked dies causes the timing mismatch of internal signals. To remove signal confliction and reduce signal skews among the stacked dies, the simultaneous process self-calibration scheme is proposed. The stacked dies using the proposed scheme detect the slowest signal among the stacked dies and internal signals are aligned with the slowest signal at the same time. The time for aligned operation is within one read loop and the scheme is turned off after calibration to reduce additional standby current. The 3D double-data rate 4 (DDR4) DRAM using the proposed scheme is operated over 2133 Mbit/s at 1.2 V.

Gallium nitride (GaN), wide bandgap semiconductor, has attracted much attention because they are projected to have much better performance than silicon. In this paper, effects of design parameters change of GaN power static induction transistor (SIT) on the electrical characteristics (breakdown voltage, on resistance) were analyzed by computer simulation. According to the analyzed results, the optimization was performed to get power GaN SIT that has 600 V class breakdown voltage. As a result, we could get optimized 600 V class power GaN SIT that has higher breakdown voltage and lower On resistance with a thin (a several micro-meters) thickness of the channel layer.

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A bolometer sensor used in an infrared thermal imaging system has many advantages on the process because it does not need a separate cooling system and its manufacturing is easy. However the sensitivity of the bolometer is low and the fixed pattern noise(FPN) is large, because the bolometer sensor is made by micro electro mechanical systems (MEMS). These problems can be fixed-by using the high performance readout integrated circuit(ROIC) with noise reduction techniques. In this paper, we propose differential delta sampling circuit to remove the mismatch noise of ROIC itself, the FPN of the bolometer. And for reduction of FPN noise, the reference signal compensation circuit which compensate the reference signal by using on-resistance of MOS transistor was proposed.

In this paper, high performance read-out integrated circuits (ROIC) for infrared (IR) image sensor applications is proposed. Because an uncooled microbolometer image sensor, used in an IR image sensor, is made by a micro electro mechanical systems process, the resistance of bolometer by each process does not appear same value under same temperature condition. This resistance variation generates a different output signal for same input by each chip. In order to improve on these drawbacks, a ROIC, which compensates for the error described above, was designed. Instead of a single input mode, a differential input mode ROIC was proposed and thus, a new circuit structure was proposed. Using results from a computer simulation, improvements such as that the effect of the process error was decreased 10---12% without an additional compensation circuit was found. Based on the simulation results, a prototype device including a ROIC and a micro bolometer with 16 × 16 cell arrays was fabricated and characterized.

As infrared light radiates, the CMOS Readout IC (ROIC) for the microbolometer typed infrared sensor detects voltage or current which is caused by the variation of resistance in the bolometer sensor. A serious problem we may have in designing the ROIC is the value of bolometer and reference resistors will be changed due to process variation. Since each pixel does not have the same value of resistance, fixed pattern noise problems happen during the sensor operations. In this paper, we propose a novel technique to compensate the fluctuation of reference resistance with taking account of process variation. By using a comparator and a cross coupled latch, we will make the value of reference resistor same as the bolometer`s.

Excellent voltage blocking capability and reliability can be obtained by trenching the field-limiting ring site which would be implanted. The trench etch step makes the junction depth deeper so that junction curvature effect and surface breakdown are less happened. The numerical analyses reveal two facts that the trenched field limiting ring has smaller maximum electric field and the electric field peak is deeper from the substrate surface, hence silicon dioxide layer can be protected. Therefore the voltage blocking capability and reliability of the new structure can be improved. The simulated results show that the trenched field limiting ring can have smaller critical electric field and accomplish near 30% increase of breakdown voltage in comparison with the conventional structure.

Current sensing in power semiconductors involves sensing of over-current in order to protect the device from harsh conditions. This technique is one of the most important functions in stabilizing power semiconductor device modules. The sense FET is very efficient method with low power consumption, fast sensing speed and accuracy. In this paper, we have analyzed the characteristics of proposed sense FET and optimized its electrical characteristics to apply conventional 450 V power MOSFET by numerical and simulation analysis. The proposed sense FET has the n-drift doping concentration , size of with , and off-state leakage current below . We offer the layout of the proposed sense FET to process actually. The offerd design and optimization methods are meaningful, which the methods can be applied to the power devices having various breakdown voltages for protection.

The metal-ferroelectric-metal (MFM) capacitor in the ferroelectric random access memory (FeRAM) embedded RFID chip is used in both the memory cell region and the peripheral analog and digital circuit area for capacitance parameter control. The capacitance value of the MFM capacitor is about 30 times larger than that of conventional capacitors, such as the poly-insulator-poly (PIP) capacitor and the metal-insulator-metal (MIM) capacitor. An MFM capacitor directly stacked over the analog and memory circuit region can share the layout area with the circuit region; thus, the chip size can be reduced by about 60%. The energy transformation efficiency using the MFM scheme is higher than that of the PIP scheme in RFID chips. The radio frequency operational signal properties using circuits with MFM capacitors are almost the same as or better than with PIP, MIM, and MOS capacitors. For the default value specification requirement, the default set cell is designed with an additional dummy cell.

The conventional IGBT has two problems to make the device taking high performance. The one is high on state voltage drop associated with JFET region, the other is low breakdown voltage associated with concentrating the electric field on the junction of between p base and n drift. This paper is about the structure to effectively improve both the lower on state voltage drop and the higher breakdown voltage than the conventional IGBT. For the fabrication of the circular trench IGBT with the circular trench layer, it is necessary to perform the only one wet oxidation step for the circular trench layer. Analysis on both the on state voltage drop and the breakdown voltage show the improved values compared to the conventional IGBT structure. Because the circular trench layer disperses electric field from the junction of between p base and n drift to circular trench, the breakdown voltage increase. The on state voltage drop decrease due to reduction of JFET region and direction changed of current path which pass through reversed layer channel. The electrical characteristics were studied by MEDICI simulation results.

It is very important to observe the change in the atomic structure of melt-quenched amorphous Ge2Sb2Te5 (GST) to discover the failure mechanism of phase-change random access memory (PRAM) devices during the reset process. We fabricated the phase-change devices and measured the initial resistance changes with various reset pulse amplitudes. For the observation of the atomic structure changes of GST thin films, we designed the specimens for transmission electron microscopy (TEM) and annealed them below and above the melting temperature of GST (Tm = 650 °C) before quenching. The annealed-and-quenched GST at 630 °C has a hexagonal structure with a grain size of about 10 nm after the partial melting. The annealed-and-quenched GST at 750 °C also has a hexagonal structure because of the latent heat. The observed atomic structures of GST are in accordance with the resistance changes inferred from the fabricated edge-contact type of PRAM cell. (© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

This paper presents a comprehensive mathematical analysis and simulation of trench IGBT with the help of PIN-PNP combinational model. Since trench IGBT is characteristically influenced by PIN diode, it may be almost impossible to analyze the trench IGBT using PNP-MOS modeling methods, even PIN-MOS techniques which neglect the hole current components coming into p-base region. A new PIN-PNP complementary cooperational model is developed in order to make up the drawbacks of existing models. It would allow us to make qualitative analysis as well as simulation about switching and on-state characteristics of 1,700 V trench IGBT. Moreover, if we improve the PIN diode effects through the optimization of trench structure, trench IGBT is expected to be one of the most promising devices in the not only high-voltage but also high speed switching device field.

Phase-change random access memory (PRAM) chip cell phase of amorphous state is rapidly changed to crystal state above 160 Celsius degree within several seconds during Infrared (IR) reflow. Thus, on-board programming method is considered for PRAM chip programming. We demonstrated the functional 512Mb PRAM with 90㎚ technology using several novel core circuits, such as metal-2 line based global row decoding scheme, PN-diode cells based BL discharge (BLDIS) scheme, and PMOS switch based column decoding scheme. The reverse-state standby current of each PRAM cell is near 10 pA range. The total leak current of 512Mb PRAM chip in standby mode on discharging state can be more than 5 mA. Thus in the proposed BLDIS control, all bitlines (BLs) are in floating state in standby mode, then in active mode, the activated BLs are discharged to low level in the early timing of the active period by the short pulse BLDIS control timing operation. In the conventional sense amplifier, the simultaneous switching activation timing operation invokes the large coupling noise between the VSAREF node and the inner amplification nodes of the sense amplifiers. The coupling noise at VSAREF degrades the sensing voltage margin of the conventional sense amplifier. The merit of the proposed sense amplifier is almost removing the coupling noise at VSAREF from sharing with other sense amplifiers.

1T1C DRAM has been facing technological and physical constraints that make more difficult their further scaling. Thus there are much industrial interests for alternative technologies that exploit new devices and concepts to go beyond the 1T1C DRAM technology, to allow better scaling, and to enlarge the memory performance. The technologies of DRAM cell are changing from 1T1C cell type to capacitor-less 1T-gain cell type for more scalable cell size. But floating body cell (FBC) of 1T-gain DRAM has weak retention properties than 1T1C DRAM. FET-type 1T-FeRAM is not adequate for long term nonvolatile applications, but could be a good alternative for the short term retention applications of DRAM. The proposed nonvolatile refresh scheme is based on utilizing the short nonvolatile retention properties of 1T-FeRAM in both after power-off and power-on operation condition.

In this paper we proposed a new source-drain structure for N-type MOSFET which can suppress the output resistance reduction of a device in saturation region due to soft break down leakage at high drain voltage when the gate is biased around relatively low voltage. When a device is generally used as a switch at high gate bias the current level is very important for the operation. but in electronic circuit like an amplifier we should mainly consider the output resistance for the stable voltage gain and the operation at low gate bias. Hence with T-SUPREM simulator we designed devices that operate at low gate bias and high gate bias respectively without a extra photo mask layer and ion-implantation steps. As a result the soft break down leakage due to impact ionization is reduced remarkably and the output resistance increases about 3 times in the device that operates at the low gate bias. Also it is expected that electronic circuit designers can easily design a circuit using the offered N-type MOSFET device with the better output resistance.

The keys to good signal integrity in a Graphic DDR3 (GDDR3) SDRAM interface for a bandwidth up to 1.4Gbps/pin are the minimization of input/output pin capacitance and the accurate control of the output data skew. The proposed pre-emphasis output buffer control scheme provides output data skew minimization without an increase of input/output pin capacitance. Compared to the conventional scheme, the output data aperture window of proposed scheme has increased by 18% and the data output skew has decreased by 48%.

In this paper, we propose and discuss the design using a simple method that reduces the fixed pattern noise(FPN) generated on the amorphous Si() bolometer. This method is applicable to an IR image sensor. This method can also minimize the size of the reference resistor in the readout integrated circuit(ROIC) which processes the signal of an IR image sensor. By connecting four bolometer cells in parallel and averaging the resistances of the bolometer cells, the fixed pattern noise generated in the bolometer cell due to process variations is remarkably reduced. Moreover an bolometer cell, which is made by a MEMS process, has a large resistance value to guarantee an accurate resistance value. This makes the reference resistor be large. In the proposed cell structure, because the bolometer cells connected in parallel have a quarter of the original bolometer`s resistance, a reference resistor, which is made by poly-Si in a CMOS process chip, is implemented to be the size of a quarter. We designed a ROIC with the proposed cell structure and implemented the circuit using a 0.35 um CMOS process.

To improve low sense margin at low voltage, we propose a negatively driven sensing (NDS) scheme and to solve the problem of WL-to-BL short leakage fail, a variable bitline reference scheme with freelevel precharged bitline (FLPB) scheme is adopted. The influence of the threshold voltage offset of NMOS and PMOS transistors in a latch type sense amplifier is very important factor these days. From evaluating the sense amplifier offset voltage distribution of NMOS and PMOS, it is well known that PMOS has larger distribution in threshold voltage variation than that of NMOS. The negativelydriven sensing (NDS) scheme enhances the NMOS amplifying ability. The offset voltage distribution is overcome by NMOS activation with NDS scheme first and PMOS activation followed by time delay. The sense amplifier takes a negative voltage during the sensing and amplifying period. The negative voltage of NDS scheme is about -0.3V to -0.6V. The performance of the NDS scheme for DRAM at the gigabit level has been verified through its realization on 1-Gb DDR2 DRAM chip.

In this paper, effects of the trench angle() on the breakdown voltage according to the process parameters of p-base region and doping concentrations of n-drift region in a Trench Gate IGBT (TIGBT) device were analyzed by computer simulation. Processes parameters used by variables are diffusion temperature, implant dose of p-base region and doping concentration of n-drift region, and aspects of breakdown voltage change with change of each parameter were examined. As diffusion temperature of the p-base region increases, depth of the p-base region increases and effect of the diffusion temperature on the breakdown voltage is very low in the case of small trench angle() but that is increases 134.8 % in the case of high trench angle(). Moreover, as implant dose of the p-base region increases, doping concentration of the p-base region increases and effect of the implant dose on the breakdown voltage is very low in the case of small trench angle() but that is increases 232.1 % in the case of high trench angle(). These phenomenons is why electric field concentrated in the trench is distributed to the p-base region as the diffusion temperature and implant dose of the p-base increase. However, effect of the doping concentration variation in the n-drift region on the breakdown voltage varies just 9.3 % as trench angle increases from to . This is why magnitude of electric field concentrated in the trench changes, but direction of that doesn`t change. In this paper, respective reasons were analyzed through the electric field concentration analysis by computer simulation.

To enhance the conversion speed more fast, we separate the determination process of MSB and LSB with the two independent ADC circuits of the Incremental Sigma Delta ADC. After the 1st Incremental Sigma Delta ADC conversion finished, the 2nd Incremental Sigma Delta ADC conversion start while the 1st Incremental Sigma Delta ADC work on the next input. By determining the MSB and the LSB independently, the ADC conversion speed is improved by two times better than the conventional Extended Counting Incremental Sigma Delta ADC. In processing the 2nd Incremental Sigma Delta ADC, the inverting sample/hold circuit inverts the input the 2nd Incremental Sigma Delta ADC, which is the output of switched capacitor integrator within the 1st Incremental Sigma Delta ADC block. The increased active area is relatively small by the added analog circuit, because the digital circuit area is more large than analog. In this paper, a 14 bit Extended Counting Incremental Sigma-Delta ADC is implemented in CMOS process with a single 2.5 V supply voltage. The conversion speed is about 150 Ksamples/sec at a clock rate of 25 MHz. The 1 MSB is 0.02 V. The active area is . The averaged power consumption is 1.7 mW.

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is , which is too large compared to of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

We have investigated pattern scaling down of silicon stamps through the oxidation technique, During oxidizing the silicon stamps, silicon dioxide that has 300 nm and 500 nm thickness was grown, and critical deformations were not observed in the patterns. There was positive effect to reduce size of patterns because vertical and horizontal patterns have different orientation. We achieved pattern reduction rate of . In addition, the formation of polymer patterns had been investigated with varied temperature and pressure conditions to improve the filling characteristics of polymers during nanoimprint lithography when pattern sizes were few micrometers. In these varied conditions, polymers had been affected by free space compensation and elastic stress relaxation for filling the cavities. Based on the results, defect control which is an important issue in the nanoimprint lithography were facilitated.

This paper presents the improved burn-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved by the burn-in process. Reliability Problem is very significant in the MCP which includes over two chips in a package because the failure of one SRAM chip has a large influence on the yield and quality of the other chips such as Flash Memory, DRAM, etc. Therefore the quality of SRAM must be guaranteed. To improve the qualify of SRAM, we applied the improved wafer level burn-in process using multi cell selection method in addition to the previously used methods and it is found to be effective in detecting particular failures. Finally, with the composition of some kinds of methods, we achieved the high quality of SRAM in MCP.

In this paper, two types of vertical SIT(Static Induction Transistor) structures are proposed to improve their electrical characteristics including the blocking voltage. Besides, the two dimensional numerical simulations were carried out using ISE-TCAD to verify the validity of the device and examine the electrical characteristics. First, a trench gate region oxide power SIT device is proposed to improve forward blocking characteristics. Second, a trench gate-source region power SIT device is proposed to obtain more higher forward blocking voltage and forward blocking characteristics at the same size. The two proposed devices have superior electrical characteristics when compared to conventional device. In the proposed trench gate oxide power SIT, the forward blocking voltage is considerably improved by using the vertical trench oxide and the forward blocking voltage is 1.5 times better than that of the conventional vertical power SIT. In the proposed trench gate-source oxide power SIT, it has considerable improvement in forward blocking characteristics which shows 1500V forward blocking voltage at -10V of the gate voltage. Consequently, the proposed trench oxide power SIT has the superior stability and electrical characteristics than the conventional power SIT.

The electrothermal characteristics of a high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) using thin silicon on insulator (SOI) and silicon on sapphire (SOS) such as thermal conductivity and sink is analyzed by MEDICI. The device simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for modeling of the thermal behavior of SOI devices. In this paper we simulated the thermal conductivity and temperature distribution of a SOI LIGBT with an insulator layer of SiO and O at before and after latch-up and verified that the SOI LIGBT with the O insulator had good thermal conductivity and reliability.

Porous silicon(PS) has received much attention as a sensitive material of chemical sensors because of its large internal surface area. In this work, we fabricated gas-sensing devices based on the porous silicon layer which could be applicable to the measurement of blood alcohol content(BAC), and estimated their electrical properties. The structure of the sensor is similar to an MIS (metal-insulator-semiconductor) diode and consists of thin Au/oxidized PS/PS/p-Si/Al, where the p-Si substrate is etched anisotropically to reduce the thickness. We measured C-V curves from two types of the samples with the PS layer treated by the different anodization current density of 60 or 100 mA/cm, in order to compare the sensitivity. As a result, the magnitude and variation of capacitances from the devices with the PS formed under the current density of 100 mA/cm were found to be more detectable due to the larger internal surface.

In this paper, we propose a phase-locked loop (PLL) with dual PFDs and a modified loop filter in which advantages of both PFDs can be combined and the trade-off between acquisition behavior and locked behavior can be achieved. By operating the appropriate PFD connected to the well-adjusted charge pump and regulating the loop bandwidth to input frequency ratio with an input divider and a modified loop filter, an unlimited error detection range, a high frequency operation, a reduced dead zone and a higher speed lock-up time can be achieved. The proposed PLL structure is designed using 1.5 μm CMOS technology with 5 V supply voltage.

In this work, we fabricated a gas-sensing device based on porous silicon(PS), and its C-V properties were investigated for sensing alcohol vapor. The structure of the sensor consists of thin Au/oxidized PS/PS/P-Si/Al, where the p-Si is etched anisotropically to be prepared into a membrane-shape. We used alcohol gases vaporized from different alcohol (or ethanol) solutions mixed with pure water at 36, similarly with an alcohol breath measurement to check drunk driving. As the result, I-V curves showed typical tunneling property, and C-V curves were shaped like those of a MIS (metal-insulator-semiconductor) capacitor, where the capacitance in accumulation was increased with alcohol vapor concentration.

The GaN, GaP, InP, Si3N4, SiO2/Si, SiC, and ZnO semiconductor nanowires were synthesized by a variety of growth methods, and they were wrapped cylindrically with amorphous aluminum oxide (Al2O3) shells. The Al2O3 was deposited on these seven different semiconductor nanowires by atomic layer deposition (ALD) at a substrate temperature of 200°C using trimethylaluminum (TMA) and distilled water (H2O). Transmission electron microscopy (TEM) images taken for the nanowires revealed that Al2O3 cylindrical shells surround uniformly all these semiconductor nanowires. Our TEM study illustrates that the ALD of Al2O3 has an excellent capability to coat any semiconductor nanowires conformally; its coating capability is independent of the chemical component, lattice structure, and growth direction of the nanowires. This study suggests that the ALD of Al2O3 on nanowires is one of the promising methods to prepare cylindrical dielectric shells in coaxially gated, nanowire field-effect transistors (FETs).

In this paper, the new dual trench gate Emitter Switched Thyristor (DTG-EST) is proposed for improving snap-back effect which leads to a lot of serious problems of device applications. Also the parasitic thyristor that is inherent in the conventional EST is completely eliminated in this structure, allowing higher maximum controllable current densities for ESTs. The conventional EST exhibits snap-back with the anode voltage and current density 2.73V and 35A/, respectively. But the proposed DTG-EST exhibits snap-back with the anode voltage and current density 0.96V and 100A/, respectively.

A new Lateral Trench Electrode Insulated Gate Bipolar Transistor (LTEIGBT) with a p+ diverter was proposed and fabricated to improve the electrical characteristics of the conventional LTIGBT. The p+ diverter was placed between anode and cathode electrodes. Because the p+ diverter region of the proposed device was enclosed trench oxide layer, the electric field centered trench-oxide layer, and punch through breakdown of LTEIGBT with p+ diverter was occurred at the high breakdown voltage. Therefore, the p+ diverter of the proposed LTIGBT didn't relate to breakdown voltage in a different way the conventional LTIGBT. As a results of device simulation, the electrical characteristics of the proposed LTEIGBT including latching current density, breakdown voltage and switching speed was superior to conventional devices. After simulation was finished, we fabricated and analyzed the proposed LTEIGBT with a p+ diverter. The maximum current of the proposed device and conventional device were 90 mA and 70 mA, respectively. Therefore, The proposed LTEIGBT with a p+ diverter is effective device for smart power IC.

A silicon-to-In2O3:Sn coated glass bonding has been developed for the package of field emission arrays fabricated on the silicon wafer, utilizing a conventional silicon-to- silicon anodic bonding using the glass layer. A 1.8 μm Pyrex #7740 glass layer was deposited on the In2O3:Sn coated glass by an electron beam evaporation. It was confirmed that the composition of the glass layer was nearly the same as that of the bulk Pyrex #7740 glass plate. In this work, bonding the silicon and In2O3:Sn coated glass was achieved at a temperature of 190 °C with an applied voltage of 60 Vdc. A secondary ion mass spectroscopy analysis was used to confirm the modeled bonding kinetics of the silicon-to-In2O3:Sn coated glass.