Search

This brief describes a self-zoom analog-to-digital converter (ADC), where zooming function is implemented by subtracting quantizer output with digital processing from input signal. Self-zoom employs a digital filter instead of a coarse ADC for zoom implementation, resulting in improved efficiency. In addition, this brief uses a 2.25-bit quantizer to achieve 5-bit self-zoom and utilizes a fast startup scheme to optimize the initiation speed. The prototype ADC was manufactured in $0.18~\mu \text{m}$ CMOS technology and occupies an area of 0.34 mm 2. In a 3.9 kHz bandwidth, the ADC achieves a DR of 114.5 dB, a SNDR of 108.7 dB, and consumes $385~\mu \text{W}$ under a 1.8V supply. This results in state-of-the-art power efficiency, in terms of FoMDR of 184.6 dB and FoMSNDR of 178.8 dB.

This brief describes a power-efficient time-domain analog front-end (AFE) for autonomous sensor nodes. This AFE combines an input pulse-width modulator (PWM) and a gated ring oscillator (GRO) to facilitate low-voltage analog building blocks. The input PWM is implemented with pseudo-differential comparators for voltage-to-time conversion, achieving high input impedance and linearity concurrently. A non-equidistant GRO works at a fixed frequency and quantizes the PWM output in time domain, realizing the first-order noise shaping. The AFE is implemented in a $0.18\mu \text{m}$ standard CMOS process. Clocked at 20kHz (500Hz bandwidth), the AFE achieves 81.6dB peak SNDR, $540{\mathrm{ mV}}_{\mathrm{ pp}}$ input signal range, and 80M $\Omega $ input impedance. The power consumption is $2.2\mu \text{W}$ at 0.8V analog and 0.6V digital supply voltages, and these correspond to a Schreier FoM of 165.2dB. Finally, the AFE properties are verified through several types of sensors.

This article presents a time-domain-controlled (TDC) single-inductor triple-output (SITO) step-up converter for portable devices with a bipolar power supply. A time-domain controller is utilized in the proposed converter to achieve a minimized delay time and thus ensure a high-conversion ratio (CR) with a switching frequency of 2 MHz. The proposed power converter employs a time-domain energy distribution (ED) balance scheme to ensure the bipolar outputs are symmetrically regulated. In addition, with the assistance of the output offset correction circuits, the load regulation of the TDC-SITO converter is greatly improved. By using an analog-to-digital converter (ADC)-assisted fast-settling loop, the converter achieves an excellent load transient response with low undershoot/overshoot voltages. Powered by a lithium-ion battery, the TDC-SITO converter can generate a bipolar power supply of $\pm$12 V and a standard 5 V output voltage, indicating a maximum CR of 8.8×. Implemented in a 180 nm bipolar-CMOS-DMOS (BCD) process, the converter achieves a peak conversion efficiency of 91.6% at an output power of 2.25 W. With a load current step of 100 mA between two output voltages of $\pm$10 V, the output voltages recover their normal values within 100 $\mu$s while the undershoot/overshoot voltages are below 160 mV. The maximum output power of the TDC-SITO converter is 9.6 W.

Envelope tracking (ET) and average power tracking (APT) have been widely used as supply modulators of power amplifiers (PAs). To meet the new challenges brought by the 5G NR standard, the symbol power tracking (SPT) technique is proposed, which is more efficient than ET and more flexible than APT. For the application of subcarrier spacing (SCS) of 15-~60kHz in the frequency range 1 (FR1), this paper proposed a buck-boost SPT supply modulator with a transition time below 1.17- $\mu \text{s}$ for 5G NR PA in the smartphone. The combination of three techniques improves the voltage transition speed. The charge-pump-based switching power modulator increases the output voltage higher than the battery voltage and offers a high voltage source for the auxiliary current paths (ACP). The ACP introduces additional currents to charge/discharge the 1- $\mu \text{F}$ output capacitor. The end-point-prediction (EPP) scheme lets the compensator convert directly from one steady state to the next. This supply modulator circuit is designed and fabricated using 0.18- $\mu \text{m}$ BCD technology. The output voltage range is 1–5-V. The maximum transition speed can be up to 0.37- $\mu \text{s}$ /V and 0.15- $\mu \text{s}$ /V for up-tracking and down-tracking, respectively.

This brief presents a tuning range extension technique for output voltage waveform-shaping single-core CMOS oscillators. First, the parasitic capacitors in previous waveform-shaping oscillators that limit the tuning range are analyzed. Next, a triple coupled LC resonator (TCLCR) is proposed to separate the differential-mode and common-mode (CM) resonance path which improves the tuning range significantly. The TCLCR is also able to establish the harmonically tuned impedance without using dedicated harmonic tuning both at CM 2rd harmonic and 3rd harmonic for oscillator’s implicit CM resonance or class-F23 operation to suppress the white noise and flicker noise conversion to phase noise. Finally, as a proof of concept, a 2.79-to-4.9 GHz class-F23 oscillator prototype covering a wide tuning range of 54.9% is designed and fabricated in a 130-nm CMOS technology. The oscillator achieves figure-of-merit with tuning range (FOMT) of 199.4/202.2 dBc/Hz, 196.3/200.9 dBc/Hz and 195/199.7 dBc/Hz at 100-kHz/1-MHz offset from 2.79, 3.83 and 4.9 GHz.

In this paper, the VLSI implementation of a low memory and low complexity architecture of JPEG2000 codec is presented. By analyzing the fix-point computation of discrete wavelet transform (DWT), a low memory implementation for lossy JPEG2000 codec is proposed. An efficient memory organization is adopted in this implementation to improve the speed of embedded block coding with optimized truncation (EBCOT) hardware accelerator. A buffered architecture is adopted in lifting based DWT to reduce the hardware cost, to achieve the higher hardware utilization and to reduce complexity of address generator. For EBCOT, a column-based coding of Tier-1 block coding engine and an effectively simplified Tier-2 coding engine are proposed. The proposed architecture of JPEG2000 codec is implemented in test camera chip that has been manufactured in 0.25um CMOS digital process. (1) Index Terms--codec, discrete wavelet transform, embedded block coding with optimized truncation, JPEG2000, VLSI.

A practical real-time auto-focus algorithm for digital camera is presented, and it improves the reliability and speed of auto-focus process, especially suitable for mega-pixel high definition camera. The proposed algorithm adopts threshold gradient and edge point count technique besides focus value function, instead of traditional two-stage climbing search algorithm that uses focus value function only. Additionally, a relative difference ratio circuit is also proposed, which can implement adaptive step size searching to increase the searching speed. By adopting the modified algorithm on the prototype of our mega-pixel digital camera, real-time auto-focus function is verified. The proposed algorithm is implemented in test camera chip that has been manufactured in 0.25um CMOS digital process. Index Terms--modified fast climbing search, focus value, threshold gradient, edge point, adaptive step size searching, relative difference ratio.