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This paperaims to explain the work developedand methodology followedwithinTask 4.2 ofWork Package 4 (WP4) of EU funded MIGRATE–Massive InteGRATion ofPower Electronic devices projectfor the assessment of short circuit protection relays under high penetrationof renewable energies and power electronic devices.This task was developed during last year 2017.The benchmark test grid for this purpose, including detailed power electronics models, has been developedin RTDS environmentin order to perform hardware in the loop tests. The analysis of the tests, which showed potential undesired behaviors of distance protection, areexplained in the following paper, and arethe focus of further research actions in WP4 studies. By making use of hardware in the loopplatformsdistance, line differential and ground directional overcurrent protection functions,runningin real protection deviceshave been tested and thoroughly analyzed.These functionswere chosen due to theirwideemployabilityin transmission systems as primary and/or backup protectionfunctions. Security and stability of the system under fault conditionsdependson the correct performance of the aforementioned protection functions.Therefore, it becomes criticalto analyze if such protection algorithms, which have been so far designed for a power system mainly fed by synchronous generators, may experience difficulties and consequently jeopardize the system security when increasing the penetration level of renewable energy, asynchronously connected to the system. To achieve the presented goals: a)Testing ofreal protection relays commonly employed by TSO’s were carried out in RTDS platforms. b)Such tests were performed in scenarios with increasing penetration levels of renewable energies,comparing the protection relay behaviors with the ones obtained in the basis scenario (100% synchronous generation). c)Analysis of the results obtained were performed by means of automatic tools developed within the project and specific oscillographydownloaded from each protection relay.

Power electronic converter (PEC) interfaced renewable energy generators (REGs) are increasingly being integrated to the power gird. With the high renewable power penetration levels, one of the key power system parameters, namely reactive power is affected, provoking steady-state voltage and dynamic/ transient stability issues. The performance of existing fault detection and phase selection scheme degrades in presence of PEC interfaced REGs power transmission network. This paper deals with a comprehensive analysis to test the performance of available distance protection, that can be used in transmission networks with high renewable power penetration levels. The performance of the different vendor distance relay is compared for different type fault in transmission line. Further, the new fast S-transform (FST) based hybrid scheme has been discussed that is capable of operating under challenging conditions. The computational complexity of FST is much lower than the S-transform. Therefore, the method is a good choice for real-time applications for the time-frequency analysis of faults in a presence of PEC interfaced REGs power transmission network. The proposed FST-based method is highly efficient and also meet the speed criteria of the relaying function when performing the task. The work is part of the EU project MIGRATE dealing with Massive Integration of Power Electronic Equipment.

This paperaims to explain the work developedand methodology followedwithinTask 4.2 ofWork Package 4 (WP4) of EU funded MIGRATE–Massive InteGRATion ofPower Electronic devices projectfor the assessment of short circuit protection relays under high penetrationof renewable energies and power electronic devices.This task was developed during last year 2017.The benchmark test grid for this purpose, including detailed power electronics models, has been developedin RTDS environmentin order to perform hardware in the loop tests. The analysis of the tests, which showed potential undesired behaviors of distance protection, areexplained in the following paper, and arethe focus of further research actions in WP4 studies. By making use of hardware in the loopplatformsdistance, line differential and ground directional overcurrent protection functions,runningin real protection deviceshave been tested and thoroughly analyzed.These functionswere chosen due to theirwideemployabilityin transmission systems as primary and/or backup protectionfunctions. Security and stability of the system under fault conditionsdependson the correct performance of the aforementioned protection functions.Therefore, it becomes criticalto analyze if such protection algorithms, which have been so far designed for a power system mainly fed by synchronous generators, may experience difficulties and consequently jeopardize the system security when increasing the penetration level of renewable energy, asynchronously connected to the system. To achieve the presented goals: a)Testing ofreal protection relays commonly employed by TSO’s were carried out in RTDS platforms. b)Such tests were performed in scenarios with increasing penetration levels of renewable energies,comparing the protection relay behaviors with the ones obtained in the basis scenario (100% synchronous generation). c)Analysis of the results obtained were performed by means of automatic tools developed within the project and specific oscillographydownloaded from each protection relay.

Commonly, Distance protection function and its settings are designed for grids largely dominated by synchronous generators. Nevertheless, today’s renewable generator farms such as; photovoltaic systems, Type 3 and Type 4 wind turbines are interconnected to the grid through partial or full-scale power electronic (PE) voltage source converters (VSC). They have the capability of fast switching in order to control their output power if necessary during an event. The control strategy and the electric circuit are substantially important in the short-circuit current characteristic in PE-based generators, In fact, it differs significantly from the conventional synchronous generators behavior which do not use PE interfaces. This paper examines the performance of the distance protection function in four different brand commercial relays in a Hardware in the Loop (HiL) environment with diverse type of faults and scenarios. The tests reveal the strengths and weaknesses of the relays. The results shown in this paper can be used as an overview of the actual protection devices performance in the present and forthcoming scenarios. The work is part of the EU project MIGRATE dealing with Massive Integration of Power Electronic Equipment.

The goal of this thesis is to analyze how MPEG-2 encoder can be optimized for real-time streaming applications Hw/Sw design re-configurable platform is chosen, where part of algorithm runs on CPU or on re-programmable hardware as a hardware accelerator. The structures is based on block level pipelining(BLP) where each frame is divided in 8X8 pixel blocks and each block is processed through the MPEG-2 video compression algorithm designed in a pipeline fashion and optimized so at to achieve maximum throughput. Here, we have designed an encoder for a Xilinx Zynq7000 series SoPC FPGA platform named as Zedboard. Initially, the encoder is designed in C and run on ARM cortex A-9 processor. This code is then profiled for ARM processor based on computational requirements. The results are analyzed and the computationally intensive subsystems are implemented as hardware accelerators to attain the desired features.

Road detection is an important machine vision problem with applications to driver assistance systems and autonomous vehicles. We carried out a literature survey of the state of the art road detection algorithms. Simulations of these algorithms were performed on road images taken from multiple datasets which revealed certain limitations such as failure under shadows or in the absence of lane markers. This is why the past few years saw the emergence of illuminant invariant based road detection techniques as the state of the art. As the name suggests, illuminant invariant is a feature which contains the colour information of the surface being captured independent of the illumination source. However, the derivation of illuminant invariant image from the RGB image makes use of the assumption that the surface being captured is lambertian. The smooth road surfaces that reflect sunlight are specular and they violate the lambertian assumption. Thus, the algorithms based on illuminant invariant feature fail to detect the road region containing specularities. The road detection algorithm functions by building a road model in the illuminant invariant feature space for each frame. The white markings that are painted over the roads in the form of zebra crossings, lane markers and arrows are not included into the road model. Hence, the algorithm fails to detect them as a part of road region. The first contribution of this thesis is to address the limitations of specularities and lane markers, thus improving the robustness of the state of the art road detection algorithm. We propose a novel specularity detection and removal method for road scenes which also removes the white markings present in the road image. The region of the image containing specularities/ markers is filled with same shade as its surrounding region. Any road detection algorithm has two aspects- the first is robustness and next is real time implementation. The second contribution of this thesis is implementation of the proposed algorithm on BeagleBone Black and Rapsberry pi-2, which are low cost, low-power single-board computers. This provides a proof-of-concept of real time computation. Thus, the thesis improves the accuracy of the state of the art path detection and provides means of real time implementation on mobile platforms.

System on Chip are processor centric platform that offer hardware, software and I/O programmability on a single chip. A SoC basically consists of two parts - The Processing System and Programmable Logic. Processing System is formed around a processor while Programmable Logic section is FPGA logic fabric. The Software Defined Radio has become a main area of interest in wireless communication technology due to its re-configurability as per requirement using software. In SDR some physical layer functionalities have very high degree of computational complexity so software can be used to define the behaviour of these elements: it is unsuitable for implementing the processing itself. The less complex functionality such as encoding, modulation etc. can be performed either in software of hardware. This is the reason that SDR calls for a close integration of processor running software to control the physical layer functionality and a high speed reconfigurable resource to manage the physical layer processing. The work done here presents the idea of partitioning hardware and software parts of software defined radio (SDR) and it also includes functionality validation by implementation on a system on chip (SoC). The design used here is a multi mode multi band digital modulator which supports BPSK and QPSK modulation schemes.

This thesis presents a Digital Costas Loop project which is used to demodulate BPSK modulated digital signal. Field Programmable Gate Array(FPGA) technology is flexible enough to perform Digital Signal Processing tasks. Direct Digital Synthesizer(DDS) is used to generate carrier frequency and is act as a local oscillator whose oscillating frequency is controlled by feedback loop. The system is analysed using logic analyser tool, ChipScope Pro, provided by Xilinx to analyse internal signals of design. Various waveforms are presented in this report for better visualization of the working of design.

There are many sensors and devices inside the satellite. All these devices need to communicate with each other, those devices can be sensor nodes or control device. According to current technology communication between different sensor nodes inside the satellite is wired, which adds the weight of the harness cable. It will be reliable if the communication between them is made wireless. Protocol satisfying communication standards at low data rate and short range wireless networking must be developed. Protocol which is suitable to meet our requirements is available in the market in commercial packages, but the commercial standard devices cannot provide the efficient functionality in space as they are not resistant to the various radiation effects taking place in space. So our aim is to design a protocol in hardware description languages which can be embedded in radiation resistant series of space Grade FPGA. The baseband transceiver proposed in this thesis uses OQPSK modulation, Pseudo noise spread spectrum is used for coding and sinusoidal pulse shaping having theoretical bandwidth efficiency of 2bits/Hz same as QPSK and OQPSK is used for baseband processing. The transceiver is initially simulated in MATLAB Simulink and then in Verilog HDL by the MODELSIM simulator.

In absence of atmospheric protection, electronics involved in space systems are exposed to radiation effects. For maintaining the proper functioning of the device in space various distinct techniques are put in use. A prominent radiation effect called Single Event Upset (SEU) is capable of changing the state of data or any component within the system. Thus, if not rectified even a single error may lead to system failure. Further, the space system must have flexibility for easy modification and upgradation. Hence, the idea of developing a fault tolerant system in FPGA based on TMR scheme stands justified. The TMR scheme, which involves execution of same program in three redundant processors with majority voters to produce output, is used for SEU mitigation. Moreover, using softcore processors and FPGA provides the space system with wide flexibility for reconfiguration. This study provides a discussion on various Radiation effects on electronics in space environment, and the techniques used in mitigation of these effects for fault tolerance. In this thesis, a new context recovery algorithm for TMR-based system to detect and correct an SEU is proposed. Further, a hardware implementation of a trivial context recovery strategy (Checkpointing and Rollback scheme) is realized in Spartan-6 FPGA SP601 Evaluation kit for a MicroBlaze soft core processor system and tested.

Nowadays, Application Specific Integrated Circuit (ASIC) design are becoming complex, even designs based of Field Programmable Gate Array (FPGA) are also complex. So it is very difficult to verify the design through waveform or log files. For that, some self-checking environment is needed to verify the functionality of the design. In my thesis work, I have worked upon developing the verification environment using System Verilog. In signal processing, most of the transformation uses multiply and addition function frequently. So Multiply-Accumulate (MAC) is the dedicated hardware to improve the speed of Digital Signal Processor (DSP). In this thesis, I have written a Verilog HDL code for MAC unit of DSP in ModelSim SE 6.3f and synthesized in Xilinx ISE 8.1i. System Verilog is used to verify MAC unit. Simulations are done using tool named ModelSim SE 6.3f of Mentor Graphics®. The constrained-randomised inputs and direct inputs are fed to the Design Under Test (DUT) as well as reference model. The output from both systems are compared to check functionality. The functional coverage and code coverage are measured for correctness of the design. The constrained random vectors and direct test cases are used to achieve higher coverage.