Search

Silicon qubits based on specific SOI FinFETs and nanowire (NW) transistors have demonstrated promising quantum properties and the potential application of advanced Si CMOS devices for future quantum computing. In this paper, for the first time, the quantum transport characteristics for the next-generation transistor structure of a stack nanosheet (NS) FET and the innovative structure of a fishbone FET are explored. Clear structures are observed by TEM, and their low-temperature characteristics are also measured down to 6 K. Consistent with theoretical predictions, greatly enhanced switching behavior characterized by the reduction of off-state leakage current by one order of magnitude at 6 K and a linear decrease in the threshold voltage with decreasing temperature is observed. A quantum ballistic transport, particularly notable at shorter gate lengths and lower temperatures, is also observed, as well as an additional bias of about 1.3 mV at zero bias due to the asymmetric barrier. Additionally, fishbone FETs, produced by the incomplete nanosheet release in NSFETs, exhibit similar electrical characteristics but with degraded quantum transport due to additional SiGe channels. These can be improved by adjusting the ratio of the channel cross-sectional areas to match the dielectric constants. [ABSTRACT FROM AUTHOR]

MOS capacitors fabricated on substrates with doping concentrations as high as 1018 cm−3 were characterized at 4.2 K. The highly doped substrate exhibited an intrinsic imaginary component of impedance at 4.2 K. The imaginary component is attributed to the time delay induced by hopping phenomena, leading to a decrease in the gate capacitance. Furthermore, we investigated the time constant associated with dopant ionization under depletion conditions and determined it to be 0.35 μ s. An equivalent circuit model of the highly doped substrate at 4.2 K is also shown. [ABSTRACT FROM AUTHOR]

This paper presents an extensive characterization of the low-frequency noise (LFN) at room temperature (RT) and cryogenic temperature (4.2K) of 40-nm bulk-CMOS transistors. The noise is measured over a wide range of bias conditions and geometries to generate a comprehensive overview of LFN in this technology. While the RT results are in-line with the literature and the foundry models, the cryogenic behavior diverges in many aspects. These deviations include changes with respect to RT in magnitude and bias dependence that are conditional on transistor type and geometry, and even an additional systematic Lorentzian feature that is common among individual devices. Furthermore, we find the scaling of the average LFN with the area and its variability to be similar between RT and 4.2K, with the cryogenic scaling reported systematically for the first time. The findings suggest that, as no consistent decrease of LFN at lower temperatures is observed while the white noise is reduced, the impact of LFN for precision analog design at cryogenic temperatures gains a more predominant role.

Quantum processors based on color centers in diamond are promising candidates for future large-scale quantum computers thanks to their flexible optical interface, (relatively) high operating temperature, and high-fidelity operation. Similar to other quantum computing platforms, the electrical interface required to control and read out such qubits may limit both the performance of the whole system and its scalability. To address this challenge, this work analyzes the requirements of the electrical interface and investigates how to efficiently implement the electronic controller in a scalable architecture comprising a large number of identical unit cells. Among the different discussed functionalities, a specific focus is devoted to the generation of the static and dynamic magnetic fields driving the electron and nuclear spins, because of their major impact on fidelity and scalability. Following the derived requirements, different system architectures, such as a qubit frequency-multiplexing scheme, are considered to identify the most power efficient approach, especially in the presence of inhomogeneity of the qubit Larmor frequency across the processor. As a result, a non-frequency-multiplexed 1-$\,\mathrm{m}\mathrm{m}^{2}$ unit-cell architecture is proposed as the optimal solution, able to address up to one electron-spin qubit and nine nuclear-spin qubits within a 3-mW average power consumption, thus establishing the baseline for the scalable electrical interface for future large-scale color-center quantum computers.

In semiconductor spin quantum bits (qubits), the radio-frequency (RF) gate-based readout is a promising solution for future large-scale integration, as it allows for a fast, frequency-multiplexed readout architecture, enabling multiple qubits to be read out simultaneously. This article introduces a theoretical framework to evaluate the effect of various parameters, such as the readout probe power, readout chain's noise performance, and integration time on the intrinsic readout signal-to-noise ratio, and thus readout fidelity of RF gate-based readout systems. By analyzing the underlying physics of spin qubits during readout, this work proposes a qubit readout model that takes into account the qubit's quantum mechanical properties, providing a way to evaluate the tradeoffs among the aforementioned parameters. The validity of the proposed model is evaluated by comparing the simulation and experimental results. The proposed analytical approach, the developed model, and the experimental results enable designers to optimize the entire readout chain effectively, thus leading to a faster, lower power readout system with integrated cryogenic electronics.

Quantum computing is a fascinating and rapidly evolving field of technology that promises to revolutionize many areas of science, engineering, and society. The fundamental unit of quantum computing is the quantum bit that can exist in two or more states concurrently, as opposed to a classical bit that can only be either 0 or 1. Any subatomic element, including atoms, electrons, and photons, can be used to implement qubits. The chosen sub-atomic elements should have quantum mechanical properties. Most commonly, photons have been used to implement qubits. Qubits can be manipulated and read by applying external fields or pulses, such as lasers, magnets, or microwaves. Quantum computers are currently suffering from various complications such as size, operating temperature, coherence problems, entanglement, etc. The realization of quantum computing, a novel paradigm that uses quantum mechanical phenomena to do computations that are not possible with classical computers, is made possible, most crucially, by the need for a quantum processor and a quantum SOC. As a result, Cryo-CMOS technology can make it possible to integrate a Quantum system on a chip. Cryo-CMOS devices are electronic circuits that operate at cryogenic temperatures, usually below 77 K (−196 °C).

This case study addresses the practical challenges associated with operating cryo-CMOS electronics. Previous research has been largely confined to impractical liquid cryogen cooling and the few under-reported examples of implementing electric cryocoolers. This study further clarifies the operation of cryo-CMOS devices cooled by electric cryocoolers. It develops and experimentally validates an analytical relation between the junction temperature and the parameters of a cryogenic system. To validate this relationship, we placed a printed circuit board in a thermal chamber, cooled it to 173 K using a Stirling cryocooler, and varied input clock frequencies. The measured values of the junction temperature were compared with calculations, which showed good prediction accuracy with a coefficient of variance of ±2%, a mean biased error of −2%, and a determination coefficient of 0.92. In addition, the measurements provided evidence for a multi-fold increase in the clock frequency of cryo-CMOS electronics. The results of this study help estimate accurately the steady-state junction temperature of cryo-CMOS devices in a wide range of cryogenic temperatures for different types of cryocoolers.

Silicon qubits based on specific SOI FinFETs and nanowire (NW) transistors have demonstrated promising quantum properties and the potential application of advanced Si CMOS devices for future quantum computing. In this paper, for the first time, the quantum transport characteristics for the next-generation transistor structure of a stack nanosheet (NS) FET and the innovative structure of a fishbone FET are explored. Clear structures are observed by TEM, and their low-temperature characteristics are also measured down to 6 K. Consistent with theoretical predictions, greatly enhanced switching behavior characterized by the reduction of off-state leakage current by one order of magnitude at 6 K and a linear decrease in the threshold voltage with decreasing temperature is observed. A quantum ballistic transport, particularly notable at shorter gate lengths and lower temperatures, is also observed, as well as an additional bias of about 1.3 mV at zero bias due to the asymmetric barrier. Additionally, fishbone FETs, produced by the incomplete nanosheet release in NSFETs, exhibit similar electrical characteristics but with degraded quantum transport due to additional SiGe channels. These can be improved by adjusting the ratio of the channel cross-sectional areas to match the dielectric constants.

This paper analyzes the performance requirements that need to be met by a clock generator applied to a low-temperature quantum computer and analyzes the negative effects on the clock generator circuit under low-temperature conditions. In order to meet the performance requirements proposed in this paper and suppress the negative effects brought about by the low temperature, a clock generator for ultra-low-temperature quantum computing is designed. This clock generator is designed by using F-CLASS Voltage Controlled Oscillator (VCO), power filter, tail resistor, differential charge pump, and other techniques. And the noise characteristics of the clock generator are analyzed by Impulse Sensitive Function (ISF) and simulation results. After simulation tests, the average power consumption of the clock generator designed in this paper is 7 mW, the phase noise is −121 dBc/Hz@1 MHz, and the jitter is 62 fs. The performance of the clock generator meets the performance requirements proposed in this paper, and the reduction in the corner frequency proves that the circuit will have better performance at low temperatures. [ABSTRACT FROM AUTHOR]

MOS capacitors fabricated on substrates with doping concentrations as high as 10 ^18 cm ^−3 were characterized at 4.2 K. The highly doped substrate exhibited an intrinsic imaginary component of impedance at 4.2 K. The imaginary component is attributed to the time delay induced by hopping phenomena, leading to a decrease in the gate capacitance. Furthermore, we investigated the time constant associated with dopant ionization under depletion conditions and determined it to be 0.35 μ s. An equivalent circuit model of the highly doped substrate at 4.2 K is also shown.

Transfer learning was examined to predict current-voltage (I-V) characteristics of MOSFETs at cryogenic temperatures. An experimental dataset was obtained from approximately 800 silicon-on-insulator MOSFETs using an automated cryogenic wafer prober to pre-train a 3-hidden-layer neural network (NN) model. Transfer learning based on the NN model was then conducted using another small dataset from 2 bulk MOSFETs. The transfer learning NN model predicted more realistic I-V characteristics and threshold voltages than a control NN model trained using only the small dataset. This study demonstrates cryogenic MOSFET characteristics prediction from a small dataset to reduce time and financial costs for developing cryo-CMOS devices.

We present a fully integrated cryogenic controller for electrostatically controlled quantum dots (QDs) implemented in a commercial 22-nm fully depleted silicon-on-insulator CMOS process and operating in a quantum regime. The QDs are realized in local well areas of transistors separated by tunnel barriers controlled by voltages applied to gate terminals. The QD arrays (QDA) are co-located with the control circuitry inside each quantum experiment cell, with a total of 28 of such cells comprising this system-on-chip (SoC). The QDA structure is controlled by small capacitive digital-to-analog converters (CDACs) and its quantum state is measured by a single-electron detector. The SoC operates at a cryogenic temperature of 3.4K. The occupied area of each QDA is $0.7 \times 0.4\mu \text{m}^2$ , while each QD occupies only $20 \times 80 \text{nm}^2$ . The low power and miniaturized area of these circuits are an important step on the way for integration of a large quantum core with millions of QDs, required for practical quantum computers. The performance and functionality of the CDAC are validated in a loop-back mode with the detector sensing the CDAC-compelled electron tunneling from the quantum point contact (QPC) node into the quantum structure. The position of the injected charge inside the QDA is intended to be controlled through the CDAC codes and programmable pulse width. Quantum effects are shown by an experimental characterization of charge injection and quantization into the QDA consisting of three coupled QDs. The charge can be transferred to a QD and sensed at the QPC, and this process is controlled by the relevant voltages and CDACs.

Operating CMOS circuits at cryogenic temperatures offers advantages of higher mobility, higher ON-current, and better subthreshold characteristics, which can be leveraged to realize high-performance CMOS circuits. However, an ultra-low-voltage operation is necessary to minimize the power consumption and to offset the cooling cost overheads. The MOSFET threshold voltages (Vt) increase at cryogenic temperatures making it challenging to achieve high performance while operating at very low voltage. Ultra-thin body and buried oxide silicon-on-insulator (UTBB-SOI)-based MOSFETs can modulate the transistor threshold voltage using the back-gate bias, unlike conventional FinFETs. This unique UTBB-SOI technology attribute has been leveraged to realize compact pseudo-static storage circuits, namely, embedded dynamic random access memory (DRAM) bitcell and a flip-flop operating at 0.2 V and 77 K. This article presents UTBB-SOI device fabrication details and calibrate experimental device characteristics with BSIM compact models. SPICE simulations suggest the feasibility of three-transistor gain-cell embedded DRAM (eDRAM) capable of reliably storing three distinct voltage levels (1.5 bits/cell) and exhibiting retention time of the order of 104 s. Furthermore, a unique pseudo-static flip-flop design is presented, which can lower the clock power by 50%, transistor count by 20%, and static power consumption by 20%.

Charge trapping is arguably the most important detrimental mechanism distorting the ideal characteristics of MOS transistors, and nonradiative multiphonon (NMP) models have been demonstrated to provide a very accurate description. For the calculation of the NMP rates at room temperature or above, simple semiclassical approximations have been successfully used to describe this intricate mechanism. However, for the computation of charge transition rates at cryogenic temperatures, it is necessary to use the full quantum mechanical description based on Fermi’s golden rule. Since this is computationally expensive and often not feasible, we discuss an efficient method based on the Wentzel–Kramers–Brillouin (WKB) approximation in combination with the saddle point method and benchmark this approximation against the full model. We show that the approximation delivers excellent results and can, hence, be used to model charge trapping behavior at cryogenic temperatures. [ABSTRACT FROM AUTHOR]

This paper presents a device matching study of a commercial 40-nm bulk CMOS technology operated at cryogenic temperatures. Transistor pairs and linear arrays, optimized for device matching, were characterized over the temperature range from 300 K down to 4.2 K. The device parameters relevant for mismatch, i.e., the threshold voltage and the current factor, were extracted, from which the change in both absolute value and variability as a function of temperature and device size were investigated. It is shown that the Pelgrom scaling law is valid also at 4.2 K and that the simplified Croon model is able to accurately predict drain-current mismatch from moderate to strong inversion over the entire temperature range. Additionally, the characterization of linear device arrays shows exacerbated edge-effects at extremely low temperatures, thus requiring the addition of dummy devices at the array boundary. The result of this study is the first model capable of predicting mismatch over a wide range of operating regions and temperatures.

This paper presents the characterization and modeling of microwave passive components in TSMC 40-nm bulk CMOS, including metal-oxide-metal (MoM) capacitors, transformers, and resonators, at deep cryogenic temperatures (4.2 K). To extract the parameters of the passive components, the pad parasitics were de-embedded from the test structures using an open fixture. The variations in capacitance, inductance and quality factor are explained in relation to the temperature dependence of the physical parameters, and the resulting insights on the modeling of passives at cryogenic temperatures are provided. Modeling the characteristics of on-chip passive components, presented for the first time down to 4.2K, is essential in designing cryogenic CMOS radio-frequency integrated circuits, a promising candidate to build the electronic interface for scalable quantum computers.

This article presents a physical model of the threshold voltage in MOSFETs valid down to 4.2 K. Interface traps close to the band edge modify the saturating temperature behavior of the threshold voltage observed in cryogenic measurements. Dopant freezeout, bandgap widening, and uniformly distributed traps in the bandgap do not change the qualitative behavior of the threshold voltage over temperature. Care should be taken because dopant freezeout results in a different physical definition of the threshold voltage. Using different definitions changes significantly the threshold current level. The proposed model is experimentally validated with measurements in large-area nMOS and pMOS devices of a commercial 28-nm bulk CMOS process down to 4.2 K. Our modeling results suggest that a pMOS-specific phenomenon in the gate stack is responsible for the non-saturating temperature behavior of the threshold voltage in pMOS devices.

Cryogenic characterization and modeling of two nanometer bulk CMOS technologies (0.16-μm and 40-nm) are presented in this paper. Several devices from both technologies were extensively characterized at temperatures of 4 K and below. Based on a detailed understanding of the device physics at deep-cryogenic temperatures, a compact model based on MOS11 and PSP was developed. In addition to reproducing the device dc characteristics, the accuracy and validity of the compact models are demonstrated by comparing time- and frequency-domain simulations of complex circuits, such as a ring oscillator and a low-noise amplifier, with the measurements at 4 K.

This paper presents an experimental investigation, compact modeling, and low-temperature physics-based modeling of a commercial 28-nm bulk CMOS technology operating at cryogenic temperatures. The physical and technological parameters are extracted at 300, 77, and 4.2 K from dc measurements made on various geometries. The simplified-EKV compact model is used to accurately capture the dc characteristics of this technology down to 4.2 K and to demonstrate the impact of cryogenic temperatures on the essential analog figures-of-merit. A new body-partitioning methodology is then introduced to obtain a set of analytical expressions for the electrostatic profile and the freeze-out layer thickness in field-effect transistors operating from deep-depletion to inversion. The proposed physics-based model relies on the drift-diffusion transport mechanism to obtain the drain current and subthreshold swing, and is validated with the experimental results. This model explains the degradation in subthreshold swing at deep-cryogenic temperatures by the temperature-dependent occupation of interface charge traps. This leads to a degradation of the theoretical limit of the subthreshold swing at deep-cryogenic temperatures.

This brief reports the analytical modeling and measurements of the inflection in the MOSFET transfer characteristics at cryogenic temperatures. Inflection is the inward bending of the drain current versus gate voltage, which reduces the current in weak and moderate inversion at a given gate voltage compared to the drift-diffusion current. This phenomenon is explained by introducing a Gaussian distribution of localized states centered around the band edge. The localized states are attributed to disorder and interface traps. The proposed model allows to extract the density of localized states at the interface from the dc current measurements. [ABSTRACT FROM AUTHOR]

A 16-nm-Lg p-type Gate-all-around (GAA) silicon nanowire (Si NW) metal oxide semiconductor field effect transistor (MOSFET) was fabricated based on the mainstream bulk fin field-effect transistor (FinFET) technology. The temperature dependence of electrical characteristics for normal MOSFET as well as the quantum transport at cryogenic has been investigated systematically. We demonstrate a good gate-control ability and body effect immunity at cryogenic for the GAA Si NW MOSFETs and observe the transport of two-fold degenerate hole sub-bands in the nanowire (110) channel direction sub-band structure experimentally. In addition, the pronounced ballistic transport characteristics were demonstrated in the GAA Si NW MOSFET. Due to the existence of spacers for the typical MOSFET, the quantum interference was also successfully achieved at lower bias.

This paper presents a physics-based analytical model for the MOS transistor operating continuously from room temperature down to liquid-helium temperature (4.2 K) from depletion to strong inversion and in the linear and saturation regimes. The model is developed relying on the 1-D Poisson equation and the drift-diffusion transport mechanism. The validity of the Maxwell–Boltzmann approximation is demonstrated in the limit to 0 K as a result of dopant freezeout in cryogenic equilibrium. Explicit MOS transistor expressions are then derived, including incomplete dopant ionization, bandgap widening, mobility reduction, and interface charge traps. The temperature dependence of the interface trapping process explains the discrepancy between the measured value of the subthreshold swing and the thermal limit at deep-cryogenic temperatures. The accuracy of the developed model is validated by experimental results on long devices of a commercial 28-nm bulk CMOS process. The proposed model provides the core expressions for the development of physically accurate compact models dedicated to low-temperature CMOS circuit simulation. [ABSTRACT FROM AUTHOR]