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10.1016/j.sse.2013.02.040, Transport mechanisms in nanocrystalline ZnO Thin Film Transistors (TFT) were investigated in a wide temperature range. The channel is located at the ZnO-SiO2 interface and controlled with a bottom gate as in a back-channel SOI MOSFET. In this work, we propose suitable mobility models that are able to provide a good agreement with the experimental results. Not only do these models account for the regular carrier transport mechanisms but they also address the physical properties of nanocrystalline ZnO films including the effect of grain boundaries. Simple parameter extraction techniques are explored and validated with numerical calculations. Our work highlights that nanocrystalline ZnO TFT provides high mobility, low threshold voltage and reasonable subthreshold swing due to good interface quality between the ZnO film and the gate insulator. The variation of these parameters at low temperature is measured and compared to the typical behavior in SOI MOSFETs.

NANOSIL Network of Excellence [NANOSIL NoE web site < www.nanosil-noe.eu >], funded by the European Commission in the 7th Framework Programme (ICT-FP7, no 216171), aims at European scale integration of the excellent European research laboratories and their capabilities in order to strengthen scientific and technological excellence in the field of nanoelectronic materials and devices for terascale integrated circuits (ICs), and to disseminating the results in a wide scientific and industrial community. NANOSIL is exploring and assessing the science and technological aspects of nanodevices and operational regimes relevant to the n+4 technology node and beyond. It encompasses projects on nanoscale CMOS and beyond-CMOS. Innovative concepts, technologies and device architectures are proposed-with fabrication down to the finest features, and utilising a wide spectrum of advanced deposition and processing capabilities, extensive characterization and very rigorous device modeling. This work is carried out through a network of joint processing, characterization and modeling platforms. This critical interaction strengthens European integration in nanoelectronics and will speed up technological innovation for the nanoelectronics of the next two to three decades., QC 20110301. International Symposium on Beyond Silicon Technology held at the 2008 EMRS Spring Meeting, Strasbourg, FRANCE, MAY 26-30, 2008

A self-aligned nickel-silicide process to reduce parasitic source and drain resistances in ultra-thin-body silicon-on-insulator (UTB-SOI)-MOSFETs is investigated. An optimized nickel-silicide process sequence including nickel sputter deposition, rapid thermal diffusion and compatible silicon nitride (Si3N4) spacers is demonstrated in UTB-SOI n-MOSFETs. Transistor on-currents and source/drain-resistivity are extracted from output and transfer characteristics and compared for various device layer thicknesses from 80 nm down to 15 nm. On-currents are improved up to a factor of 100 for the thinnest transistors by the introduction of self-aligned NiSi. Front and back gate interface qualities are extracted to evaluate their potential impact on mobility and on-currents specifically for ultra-thin devices., QC 20120227

We report unusual gate current variations with gate bias and time in accumulation regime. Measurements and simulations show the importance of the time-dependent floating body potential in both partially and fully depleted SOI MOSFETs. These variations during front-gate voltage scan and the resulting transient gate current are discussed as a combination of several mechanisms such as capacitive coupling, SRH generation, band-to-band tunneling and impact ionization. The gate current behavior is important for EEPROMs and depends on the device geometry and operating conditions., Anglais

The aim of this paper is to present a thorough examination and update the electrical properties of recent silicon on sapphire wafers., Prepared in collaboration with LPCS/ENSERG, Grenoble, Cedex France. Pub in: 9th International Symposium on Silicon-on-Insulator Technology and Devices, 195th Meeting of the Electrochemical Society, Seattle, Washington, May 2-5, 1999.

A new method for;extracting the carrier recombination lifetime in dual-gate silicon-on-insulator (SOI) structures is proposed. The experiment, model, and numerical simulations indicate that an excess forward current is obtained when carrier recombination occurs in the whole film volume.

Simultaneous measurements of drain and gate currents in short-channel accumulation-mode SOI p-MOSFET'MOs demonstrate that a latch mechanism may occur in these devices and induce an anomalous behavior of the hot-electron gate current: distortion of I(g)(V(g)) curves, hysteresis and excessively high gate current values. 2-D MEDICI simulations based on the lucky-electron model qualitatively reproduce the measurements in the latch regime, and explain the unusual gate current dependence on drain and gate biases. The results are of relevance for reliability and modeling issues.