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The impedance, capacitance and conductance of deionized water-glucose polar solution is measured by employing impedance spectroscopy and a quasi-oscillatory nature of variation with glucose content in the solution is observed. Such quasi-oscillatory nature is attributed to the randomly distributed water-water, water-glucose and glucose-glucose dipole interactions at the molecular level in the solution. A relevant analytical model is developed on the basis of such random distribution of the molecular dipoles and the experimental data agree well with those obtained from the theoretical model. The electrical parameters are measured in the frequency range of 100Hz to 4MHz for the volume fractions of glucose with respect to water in the range of 0.1 to 0.5. The impedance, capacitance and conductance are obtained to be in the range of 1.03 kΩ – 112 kΩ, 34.9 pF – 1.66 nF, and 8.95 μS – 52.9 μS respectively for the glucose volume fraction range considered.

High interfacial area, less surface defects and wide light absorption capability of core-shell nanowire heterojunctions are broadly accepted as a potential candidate for self-biased, high-speed photodetectors. In the current study, Y:ZnO–Ga2O3 core-shell nanowires' heterojunctions are fabricated by employing sequential double-step chemical bath deposition (CBD) and radio -frequency (RF) sputtering techniques on Si substrate. The ultra-thin highly transparent Ga2O3 (~ 15 nm) layer reduces the surface states of Y:ZnO nanowires in a significant amount and such core-shell heterojunction deals with the development of low power white light-responsive detectors by combining Y:ZnO and Ga2O3. The crystallinity, structure, chemical states and light absorption properties of the Y:ZnO–Ga2O3 core-shell nanowires are analysed in detail by using XRD, FESEM, HRTEM, EDS, XPS and UV-Visible spectroscopy. The fabricated core-shell Y:ZnO–Ga2O3 nanowire/Si heterojunction exhibits p–n junction behaviour and it exhibits self-powered photoresponse under Xe lamp with AM 1.5 G (100 W/cm2) filter. A low dark current of ~ 1.74 × 10− 11 A, high photo-to-dark current ratio of 3.2 × 104 and rapid response speed of < 1 s are achieved from such core-shell heterojunction device and relevant photo-carrier generation mechanism is considered from energy band diagram. Therefore, current study provides a technological route to fabricate the next-generation self-powered core-shell heterojunction devices for photo-sensing applications. [ABSTRACT FROM AUTHOR]

An analytical model of threshold voltage for globally strained Si/SiGe CMOS devices using dual-channel architecture is proposed. Findings reveal that the model successfully provides a physical insight for the variation of threshold voltage for both n- and p-MOSFETs in dual-channel architecture.

A new semianalytical model for the energy dispersion of the holes in the inversion layer of pMOS transistors, which could be used to calculate the effective mobility of pMOS transistors, is presented.

The effects of Ge content in the virtual substrates (VS) and strained-Si thickness on the strained Si/Si[O.sub.2] interface are investigated. The results have shown that a minimum strained-Si layer thickness of 5.0 nm is required to obtain a good strained Si/Si[O.sub.2] interface quality for surface channel strained-Si-n-MOSFETs, which is fabricated by using a high thermal budget CMOS process.

The results comparing strained-Si-SiGe n-channel MOSFET performance of single- and dual-surface channel devices fabricated using 15% Ge content SiGe virtual substrates have been presented. The compromised performance enhancements of the dual-channel devices are attributed to greater interface roughness and increased Ge diffusion resulting from the Si(sub 0.7)Ge(sub 0.3) buried channel layer.

On-state and off-state performance of strained-Si-SiGe n-channel MOSFETs are investigated as a function of SiGe (silicon-germanium) virtual substrate alloy composition. Off-state characteristics are found to be more sensitive to strain relaxation than on-state characteristics.

Performance enhancements of upto 170% in drain current, maximum transconductance, and field-effect mobility for nMOSFETs fabricated with strained-Si channels compared with identically processed bulk Si MOSFETs are presented.

In this paper, a high-quality crystalline thin film (~10 nm) of titanium dioxide (TiO2-II) phase is grown on p-GaAs (100) substrate by employing the vapor--liquid--solid method. The formation of crystalline TiO2-II films is confirmed by X-ray diffraction study. A very small rms surface roughness of ~1 nm has been measured from atomic force microscopy. The capacitance--voltage characteristics of Al/TiO2-II/GaAs metal--oxide--semiconductor (MOS) capacitor indicate the growth of excellent thin film of TiO2-II phase with high effective dielectric constant of 28, 35, 65, and 14 for the as-grown and 600 °C, 625 °C, and 650 °C annealed samples, respectively. An effective oxide thickness of ~0.7 nm, a negligible hysteresis of 10 mV, very small frequency dispersion of 3.5%, and a reduced gate leakage current of ~10-13 A/μm² at +2 V are achieved due to annealing in the temperature range of 600 °C-625 °C. Thus, this paper provides a cost-effective novel alternative technique to grow high-quality TiO2-II films on GaAs substrate which may be used as the reliable high-k gate dielectrics on III-V semiconductor-based MOS devices and circuits. [ABSTRACT FROM AUTHOR]

The combined impact of process- and substrate-induced stress has been analyticallymodeled for a rectangular fin inserted into an insulator-on-silicon (IOS) substrate. Stress estimation and profiling are performed for different fractional insertion of the fin into the IOS substrate and the induced stress values are observed to saturate for ≥1/3 of the fin insertion. Therefore, a one-third of inserted Si fin is used to estimate the induced stress by following a standard FinFET process flow. Uniaxial compressive stress as high as 4.6 GPa has been obtained, and it has also been observed that the hole mobility can be enhanced to a significantly high value by judiciously choosing the gate dielectrics and fractional insertion of the fin. Thereby, the design of symmetric CMOS by using such mobility-enhanced p-FinFET is possible. Moreover, the current--voltage characteristics of such strain-engineered p-FinFETs exhibit improved drain-induced barrier lowering and subthreshold swing and ~45% enhancement of drain current. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model of threshold voltage VT for globally strained Si/SiGe CMOS devices using a dual-channel architecture is proposed. Since band parameters modify VT, they are calculated and generalized for different Ge contents in a Si1-xGex film grown on relaxed Si1-xGex virtual substrates (x, y < 0.7). A model for predicting VT is then developed by considering device geometry and material properties, including band parameters, permittivity, and channel and substrate doping concentrations. VT lowering due to short-channel effects is included by incorporating a voltage-doping transformation. Accuracy of the model is verified by comparing the model with the results of technology computer-aided design simulations and experiments. The model provides a physical insight for the variation of VT for both n- and p-MOSFETs in a dual-channel architecture, and it can be generalized to be applicable to single-channel devices as well. [ABSTRACT FROM AUTHOR]

This paper presents the first results and analysis of strained Si n-channel MOSFETs fabricated on thin SiGe virtual substrates. Significant improvements in electrical performance are demonstrated compared with Si control devices. The impact of SiGe device self-heating is compared for strained Si MOSFETs fabricated on thin and thick virtual substrates. This paper demonstrates that by using high-quality thin virtual substrates, the compromised performance enhancements commonly observed in short-gate-length MOSFETs and high-bias conditions due to self-heating in conventional thick virtual substrate devices are eradicated. The devices were fabricated with a 2.8-nm gate oxide and included NiSi to reduce the parasitic series resistance. The strained layers grown on the novel substrates comprising 20% Ge did not relax during fabrication. Good ON-state performance, OFF-state performance, and cross-wafer uniformity are demonstrated. The results show that thin virtual substrates have the potential to circumvent the major issues associated with conventional virtual substrate technology. A promising solution for realizing high-performance strained Si devices suitable for a wide range of applications is thus presented. [ABSTRACT FROM AUTHOR]