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Hardware resource fragmentation is a common issue in data centers. Traditional solutions based on migration or overcommitment are unacceptably slow, and modern commercial or research solutions like Spot VM may reduce or evict VM’s resources anytime.We propose an alternative solution that does not suffer from these drawbacks, the Aggregate VM.We introduce a new distributed hypervisor design, the resource-borrowing hypervisor, which creates Aggregate VMs: distributed VMs that temporarily aggregate fragmented resources belonging to different host machines, which require mobility of virtual CPUs, memory and IO devices.We implement a prototype, FragVisor, which runs guest software transparently.We also propose minimal modifications to the guest OS that can enable significant performance gains. We evaluate FragVisor over a set of microbenchmarks and IaaS-style real applications. Although Aggregate VMs are not a perfect fit for every type of applications, some workloads enjoy significant speedups compared to overcommitted scenarios (up to 3.9x with 4 distributed vCPUs).We further demonstrate that FragVisor is faster than a state-of-the-art competitor, GiantVM (up to 2.5x). Published version

WebAssembly is gaining more and more popularity, finding applications beyond the Web browser -- for which it was initially designed for.However, its performance, which developers aimed at being comparable to native, requires further tuning, and has not been extensively studied to pinpoint the cause of various overheads.This paper identifies that WebAssembly's unique safety mechanisms, the major one being bounds-checked memory accesses, may introduce up to a 650% overhead.Therefore, we evaluate four popular WebAssembly runtimes against native compiled code.These runtimes have been enriched with modern bounds checking mechanisms and run on three different ISAs, including x86-64, Armv8 and RISC-V RV64GC.We show that performance-oriented runtimes are able to achieve performance within 20% of native on x86_64 platforms, and 35% for Armv8. On RISC-V the V8 runtime can achieve a 17% overhead over native code for simple numeric kernels.For simple numerical kernels, we have shown that there is no significant difference in the WebAssembly performance compared to native code across different ISAs.We also show that in the case of multithreaded scaling of the tested runtimes, which might for example be used to quickly scale up serverless instances for a single function without the overhead of spawning new processes, the default approach taken by WAVM, Wasmtime, and V8 of using the mprotect syscall to resize memory can cause excessive locking in the Linux kernel and so present an alternative userfaultfd-based solution to mitigate this issue.We share our results, and the tools and scripts under an open source license for other researchers to replicate our results, and monitor the progress that WebAssembly runtimes make as this technology evolves.

Edge computing is a recent computing paradigm that brings cloud services closer to the client. Among other features, edge computing offers extremely low client/server latencies. To consistently provide such low latencies, services should run on edge nodes that are physically as close as possible to their clients. Thus, when the physical location of a client changes, a service should migrate between edge nodes to maintain proximity. Differently from cloud nodes, edge nodes integrate CPUs of different Instruction Set Architectures (ISAs), hence a program natively compiled for a given ISA cannot migrate to a server equipped with a CPU of a different ISA. This hinders migration to the closest node. We introduce H-Container, a system that migrates natively compiled containerized applications across compute nodes featuring CPUs of different ISAs. H-Container advances over existing heterogeneous-ISA migration systems by being (a) highly compatible – no user’s source-code nor compiler toolchain modifications are needed; (b) easily deployable – fully implemented in user space, thus without any OS or hypervisor dependency, and (c) largely Linux-compliant – it can migrate most Linux software, including server applications and dynamically linked binaries. H-Container targets Linux and its already-compiled executables, adopts LLVM, extends CRIU, and integrates with Docker. Experiments demonstrate that H-Container adds no overheads during program execution, while 10–100 ms are added during migration. Furthermore, we show the benefits of H-Container in real-world scenarios, demonstrating, for example, up to 94% increase in Redis throughput when client/server proximity is maintained through heterogeneous container migration.

Datacenter servers are increasingly heterogeneous: from x86 host CPUs, to ARM or RISC-V CPUs in NICs/SSDs, to FPGAs. Previous works have demonstrated that migrating application execution at run-time across heterogeneous-ISA CPUs can yield significant performance and energy gains, with relatively little programmer effort. However, FPGAs have often been overlooked in that context: hardware acceleration using FPGAs involves statically implementing select application functions, which prohibits dynamic and transparent migration. We present Xar-Trek, a new compiler and run-time software framework that overcomes this limitation. Xar-Trek compiles an application for several CPU ISAs and select application functions for acceleration on an FPGA, allowing execution migration between heterogeneous-ISA CPUs and FPGAs at run-time. Xar-Trek’s run-time monitors server workloads and migrates application functions to an FPGA or to heterogeneous-ISA CPUs based on a scheduling policy. We develop a heuristic policy that uses application workload profiles to make scheduling decisions. Our evaluations conducted on a system with x86-64 server CPUs, ARM64 server CPUs, and an Alveo accelerator card reveal 88%-1% performance gains over no-migration baselines. Published version

International audience; Nowadays, there is a shift in the deployment model of Cloud and Edge applications. Applications are now deployed as a set of several small units communicating with each other - the microservice model. Moreover, each unit - a microservice, may be implemented as a virtual machine, container, function, etc., spanning the different Cloud and Edge service models including IaaS, PaaS, FaaS. A microservice is instantiated upon the reception of a request (e.g., an http packet or a trigger), and a rack-level or data-center-level scheduler decides the placement for such unit of execution considering for example data locality and load balancing. With such a configuration, it is common to encounter scenarios where different units, as well as multiple instances of the same unit, may be running on a single server at the same time.When multiple microservices are running on the same server not necessarily all of them are doing actual processing, some may be busy-waiting - i.e., waiting for events (or requests) sent by other units. However, these "idle" units are consuming CPU time which could be used by other running units or cloud utility functions on the server (e.g., monitoring daemons). In a controlled experiment, we observe that units can spend up to 20% - 55% of their CPU time waiting, thus a great amount of CPU time is wasted; these values significantly grow when overcommitting CPU resources (i.e., units CPU reservations exceed server CPU capacity), where we observe up to 69% - 75%. This is a result of the lack of information/context about what is running in each unit from the server CPU scheduler perspective.In this paper, we first provide evidence of the problem and discuss several research questions. Then, we propose an handful of solutions worth exploring that consists in revisiting hypervisor and host OS scheduler designs to reduce the CPU time wasted on idle units. Our proposal leverages the concepts of informed scheduling, and monitoring for internal and external events. Based on the aforementioned solutions, we propose our initial implementation on Linux/KVM.

With the idea of exploiting all the computational resources that an IoT environment with multiple interconnected devices offers, serverkernel is presented as a new operating system architecture that blends ideas from distributed operating systems, Unikernel, and LWK. These concepts are mixed with a server in which a user can remotely offload computations and get the result. This single space-address operating system (OS) can be interpreted as a bare-metal OS in which only drivers for CPU, network, and accelerators are required in order to provide service.To demonstrate the advantages of serverkernel, jonOS, an open-source C implementation of this architecture for Raspberry Pi, is provided. Compared with commercial architectures used in IoT devices, serverkernel achieves an improvement ratio of 1.5 in CPU time, 2.5 in real-time, and around 9 times better in network speed.

Edge computing is a recent computing paradigm that brings cloud services closer to the client. Among other features, edge computing offers extremely low client/server latencies. To consistently provide such low latencies, services need to run on edge nodes that are physically as close as possible to their clients. Thus, when a client changes its physical location, a service should migrate between edge nodes to maintain proximity. Differently from cloud nodes, edge nodes are built with CPUs of different Instruction Set Architectures (ISAs), hence a server program natively compiled for one ISA cannot migrate to another. This hinders migration to the closest node.We introduce H-Container, which migrates natively-compiled containerized applications across compute nodes featuring CPUs of different ISAs. H-Container advances over existing heterogeneous-ISA migration systems by being a) highly compatible – no source code nor compiler toolchain modifications are needed; b) easily deployable – fully implemented in user space, thus without any OS or hypervisor dependency, and c) largely Linux compliant – can migrate most Linux software, including server applications and dynamically linked binaries. H-Container targets Linux, adopts LLVM, extends CRIU, and integrates with Docker. Experiments demonstrate that H-Container adds no overhead on average during program execution, while between 10ms and 100ms are added during migration. Furthermore, we show the benefits of H-Container in real scenarios, proving for example up to 94% increase in Redis throughput when unlocking heterogeneity.

Heterogeneous-ISA computing platforms have become ubiquitous, and will be used for diverse workloads which render static mappings of computation to processors inadequate. Dynamic mappings which adjust an application's usage in consideration of platform workload can reduce application latency and increase throughput for heterogeneous platforms. We introduce AIRA, a compiler and runtime for flexible execution of applications in CPU-GPU platforms. Using AIRA, we demonstrate up to a 3.78x speedup in benchmarks from Rodinia and Parboil, run with various workloads on a server-class platform. Additionally, AIRA is able to extract up to an 87 percent increase in platform throughput over a static mapping.

Kernel information leak vulnerabilities are a major security threat to production systems. Attackers can exploit them to leak confidential information such as cryptographic keys or kernel pointers. Despite efforts by kernel developers and researchers, existing defenses for kernels such as Linux are limited in scope or incur a prohibitive performance overhead. In this paper, we present kMVX, a comprehensive defense against information leak vulnerabilities in the kernel by running multiple diversified kernel variants simultaneously on the same machine. By constructing these variants in a careful manner, we can ensure they only show divergences when an attacker tries to exploit bugs present in the kernel. By detecting these divergences we can prevent kernel information leaks. Our kMVX design is inspired by multi-variant execution (MVX). Traditional MVX designs cannot be applied to kernels because of their assumptions on the run-time environment. kMVX, on the other hand, can be applied even to commodity kernels. We show our Linux-based prototype provides powerful protection against information leaks at acceptable performance overhead (20-50% in the worst case for popular server applications).

The ITER Heating Neutral Beam injectors will be implemented in three steps: development of the ion source prototype, development of the full injector prototype, and, finally, construction of up to three ITER injectors. The first two steps will be carried out in the ITER neutral beam test facility under construction in Italy. The ion source prototype, referred to as SPIDER, which is currently in the development phase, is a complex experiment involving more than 20 plant units and operating with beam-on pulses lasting up to 1 h. As for control and data acquisition it requires fast and slow control (cycle time around 0.1 ms and 10 ms, respectively), synchronization (10 ns resolution), and data acquisition for about 1000 channels (analogue and images) with sampling frequencies up to tens of MS/s, data throughput up to 200 MB/s, and data storage volume of up to tens of TB/year. The paper describes the architecture of the SPIDER control and data acquisition system, discussing the SPIDER requirements and the ITER CODAC interfaces and specifications for plant system instrumentation and control.

The real-time control system of RFX-mod, in operation since 2005, has been successful and has allowed several important achievements in the RFX physics research program. As a consequence of this fact, new control algorithms are under investigation, which are more demanding in terms of both enhanced computing power and reduced system latency, currently around 1.5 ms. For this reason, a major upgrade of the system is being considered, and a new architecture has been proposed, taking advantage of the rapid evolution of computer technology in the last years. The central component of the new architecture is a Linux-based multicore server, where individual cores replace the VME computers. The server is connected to the I/O via PCI-e based bus extenders, and every PCI-e connection is managed by a separate core. The system is supervised by MARTe, a software framework for real-time applications written in C++ and developed at JET and currently used for the JET vertical stabilization and in other fusion devices.

The PCU-Project [1] launched for the enhancement of the vertical stabilisation system at JET required the design of a new real-time control system with the challenging specifications of 2 Gops and a cycle time of 50 μ s. The RTAI based architecture running on an x86 multi-core processor technology demonstrated to be the best platform for meeting the high requirements. Moreover, on this architecture thanks to the smart allocation of the interrupts it was possible to demonstrate simultaneous data streaming at 50 MBs on Ethernet while handling a real-time 100 kHz interrupt source with a maximum jitter of just 3 μ s. Because of the memory limitation imposed by 32 bit version Linux running in kernel mode, the RTAI-based new controller allows a maximum practical data storage of 800 MB per pulse. While this amount of data can be accepted for JET normal operation it posed some limitations in the debugging and commissioning of the system. In order to increase the capability of the data acquisition of the system we have designed a mechanism that allows continuous full bandwidth ( 56 MB/s) data streaming from the real-time task (running in kernel mode) to either a data collector (running in user mode) or an external data acquisition server. The exploited architecture involves a peer to peer mechanisms where the sender running in RTAI kernel mode broadcasts large chunks of data using UDP packets, implemented using the ‘fcomm’ RTAI extension [2] , to a receiver that will store the data. The paper will present the results of the initial RTAI operating system tests, the design of the streaming architecture and the first experimental results.

The Plasma Control Upgrade (PCU) enhancement project was setup with the aim of effectively increasing the JET operating space by both improving the Vertical Stabilization System Controller and by procuring a more powerful Radial Field Amplifier. The hardware and software technological advancements that have been used allowed to implement a 200 channel, 20 kHz control system with less than 2 μ s jitter and over 2 G o p s of processing capability. The software design, driven by an object oriented analysis, enabled a good compromise between real-time performances and reliability–maintainability objectives. The first operational experience of the system will be presented.

A new framework for the development and execution of real-time codes is currently being developed and commissioned at JET. The foundations of the system are Linux, the Real Time Application Interface (RTAI) and a wise exploitation of the new i386 multi-core processors technology. The driving motivation was the need to find a real-time operating system for the i386 platform able to satisfy JET Vertical Stabilisation Enhancement project requirements: 50 μs cycle time. Even if the initial choice was the VxWorks operating system, it was decided to explore an open source alternative, mostly because of the costs involved in the commercial product. The work started with the definition of a precise set of requirements and milestones to achieve: Linux distribution and kernel versions to be used for the real-time operating system; complete characterization of the Linux/RTAI real-time capabilities; exploitation of the multi-core technology; implementation of all the required and missing features; commissioning of the system. Latency and jitter measurements were compared for Linux and RTAI in both user and kernel-space. The best results were attained using the RTAI kernel solution where the time to reschedule a real-time task after an external interrupt is of 2.35 ± 0.35 μs. In order to run the real-time codes in the kernel-space, a solution to provide user-space functionalities to the kernel modules had to be designed. This novel work provided the most common functions from the standard C library and transparent interaction with files and sockets to the kernel real-time modules. Kernel C++ support was also tested, further developed and integrated in the framework. The work has produced very convincing results so far: complete isolation of the processors assigned to real-time from the Linux non real-time activities, high level of stability over several days of benchmarking operations and values well below 3 μs for task rescheduling after external interrupt. From being the alternative option, RTAI has been finally chosen as the platform for the project. A first stable version of the framework has been integrated on the JET system and is already being commissioned. It will be soon be used on the Vertical Stabilisation Enhancement for the Plasma Control Upgrade (PCU) project at JET.

Load balancing is one of the main challenges in a Virtual Machine (VM) Environment in order to ensure equal utilization of all the available resources while avoiding overloading a subset of machines. In this paper, we propose an efficient load balancing strategy based on VM live migration. Unlike previous work, our strategy records the history of mappings to inform future placement decisions. We also apply a workload-adaptive live migration algorithm in order to minimize VM downtime and improve the user experience. The evaluation shows that our load balancing technique is faster than previous approaches, thus reducing the decision generating latency by as much as 79%. Furthermore, the results also show that we provide minimal downtime. Compared with competitors, our proposed migration mechanism reduces the downtime by up to 73%.

EPICS is used worldwide to build distributed control systems for scientific experiments. The EPICS software suite is based around the Channel Access (CA) network protocol that allows the communication of different EPICS clients and servers in a distributed architecture. Servers are called Input/Output Controllers (IOCs) and perform real-world I/O or local control tasks. EPICS IOCs were originally designed for VxWorks to meet the demanding real-time requirements of control algorithms and have lately been ported to different operating systems. The MARTe framework has recently been adopted to develop an increasing number of hard real-time systems in different fusion experiments. MARTe is a software library that allows the rapid and modular development of stand-alone hard real-time control applications on different operating systems. MARTe has been created to be portable and during the last years it has evolved to follow the multi-core evolution.In this paper we review several implementation differences between EPICS IOC and MARTe. We dissect their internal data structures and synchronization mechanisms to understand what happens behind the scenes. Differences in the component based approach and in the concurrent model of computation in EPICS IOC and MARTe are explained. Such differences lead to distinct time models in the computational blocks and distinct real-time capabilities of the two frameworks that a developer must be aware of.

This paper reports the highlights of the RFX-mod fusion science programme since the last 2010 IAEA Fusion Energy Conference. The RFX-mod fusion science programme focused on two main goals: exploring the fusion potential of the reversed field pinch (RFP) magnetic configuration and contributing to the solution of key science and technology problems in the roadmap to ITER. Active control of several plasma parameters has been a key tool in this endeavour. New upgrades on the system for active control of magnetohydrodynamic (MHD) stability are underway and will be presented in this paper. Unique among the existing fusion devices, RFX-mod has been operated both as an RFP and as a tokamak. The latter operation has allowed the exploration of edge safety factor q edge < 2 with active control of MHD stability and studies concerning basic energy and flow transport mechanisms. Strong interaction has continued with the stellarator community in particular on the physics of helical states and on three-dimensional codes. © 2013 IAEA, Vienna.