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The chemical vapor deposition of silicon on a patterned silicon substrate leads to the formation of 3D microcrystals, which, due to their inclined top facets and high aspect ratio, produce a light‐trapping effect enhancing the optical absorption in the near‐infrared (NIR). In this work, it is demonstrated that Si microcrystals can form the building blocks of a new class of NIR sensitive photodetectors operating in a linear or avalanche regime. Microcrystal‐based devices are designed by coupling a 2D kinetic‐growth model with a Poisson drift‐diffusion solver and fabricated by combining electron beam lithography and low‐energy plasma‐enhanced chemical vapor deposition (LEPECVD). The optoelectronic properties of microcrystal‐based p–i–n photodiodes are investigated both theoretically and experimentally by means of finite‐difference time‐domain (FDTD) simulations and responsivity measurements. At 1000 nm wavelength, the responsivity of microcrystal‐based devices is six times higher than that of an equivalent mesa diode. Moreover, the photocurrent gains of Si microcrystals operating as an avalanche photodiode (APD), at the same wavelength, reaches 2 × 104 demonstrating the potentialities of substrate patterning, combined with epitaxial growth, for amplified photodetection applications. [ABSTRACT FROM AUTHOR]

The recently developed precession electron diffraction (PED) technique in scanning transmission electron microscopy has been used to elucidate the local strain distribution and crystalline misorientation in a CMOS fabricated strained Ge microdisk structure grown on a Si substrate. Tensile strained Ge and GeSn structures are considered to be potential CMOS compatible optical sources, as both Sn alloying and strain can lead to a direct band-structure and lasing. The ability to take nanometer resolution, experimental measurements of the cross-sectional strain distribution, is important to understand modal gain and, therefore, ultimate device performance. In this work, we demonstrate PED techniques to measure the cross-sectional strain field in tensile Ge microdisks strained by SiN stressors. The strain maps are interpreted and compared with a finite element model of the strain in the investigated structure, which shows good agreement, and, therefore, highlights the applicability of PED techniques for mapping strained photonic structures. The technique also allows for the observation of strain relaxation due to dislocation pileup, further demonstrating the benefit of such experimental techniques. [ABSTRACT FROM AUTHOR]

Flash memory devices--that is, non-volatile computer storage media that can be electrically erased and reprogrammed--are vital for portable electronics, but the scaling down of metal-oxide-semiconductor (MOS) flash memory to sizes of below ten nanometres per data cell presents challenges. Molecules have been proposed to replace MOS flash memory (1), but they suffer from low electrical conductivity, high resistance, low device yield, and finite thermal stability, limiting their integration into current MOS technologies. Although great advances have been made in the pursuit of molecule-based flash memory (2), there are a number of significant barriers to the realization of devices using conventional MOS technologies (3-7). Here we show that core-shell polyoxometalate (POM) molecules (8) can act as candidate storage nodes for MOS flash memory. Realistic, industry-standard device simulations validate our approach at the nanometre scale, where the device performance is determined mainly by the number of molecules in the storage media and not by their position. To exploit the nature of the core-shell POM clusters, we show, at both the molecular and device level, that embedding [[[(Se(IV)[O.sub.3]).sub.2]].sup.4-] as an oxidizable dopant in the cluster core allows the oxidation of the molecule to a [[Se[(V).sub.2][O.sub.6]].sup.2-] moiety containing a {Se(v)-Se(v)} bond (where curly brackets indicate a moiety, not a molecule) and reveals a new 51 oxidation state for selenium. This new oxidation state can be observed at the device level, resulting in a new type of memory, which we call 'write-once-erase'. Taken together, these results show that POMs have the potential to be used as a realistic nanoscale flash memory. Also, the configuration of the doped POM core may lead to new types of electrical behaviour (9-11). This work suggests a route to the practical integration of configurable molecules in MOS technologies as the lithographic scales approach the molecular limit (12)., To engineer the flash memory devices, we selected a core-shell POM 'Dawson-like' archetype as the functional part of the switching node with the general formula [[[M.sub.18][O.sub.54][(X[O.sub.n]).sup.2]].sup.m-] (where M = Mo [...]

The design, fabrication, and characterization of a silicon nitride waveguide polarization rotator and polarization beam splitter that operate with a polarization extinction ratio (PER) of ∼30 dB at the rubidium atomic transition of 780 nm wavelength are demonstrated. These polarization devices are fabricated on the same chip using a self-aligned process for integration of the rib and ridge waveguide structures. The polarization rotator is based on the mode evolution approach using adiabatic tapers and demonstrates a PER of ≥20 dB over a 100 nm bandwidth (730–830 nm wavelengths) with an insertion loss (IL) ≤1 dB. The polarization beam splitter is based on a cascaded tapered asymmetric directional coupler with phase matching between the fundamental and higher order TM modes, whereas the TE mode is separated by the through port. This provides a PER ≥ 20 dB with IL ≤ 1 dB over a 50 nm bandwidth for the cross port and a PER ≥ 15 dB with an IL ≤ 1 dB over an 18 nm bandwidth for the through port. These polarization control waveguide devices will enable photonic integrated circuits for saturated absorption spectroscopy of atomic vapors for laser stabilization on-chip. [ABSTRACT FROM AUTHOR]

A new design for SiGe waveguides with very low propagation losses that would make lasing possible is described. The system offers the advantage of the dispensing with buried or double metal fabrication route, thus requiring on the far simpler surface processing.

The results comparing strained-Si-SiGe n-channel MOSFET performance of single- and dual-surface channel devices fabricated using 15% Ge content SiGe virtual substrates have been presented. The compromised performance enhancements of the dual-channel devices are attributed to greater interface roughness and increased Ge diffusion resulting from the Si(sub 0.7)Ge(sub 0.3) buried channel layer.

We report electroluminescence originating from L-valley transitions in n-type Ge/Si0.15Ge0.85 quantum cascade structures centered at 3.4 and 4.9 THz with a line broadening of Δ f / f ≈ 0.2. Three strain-compensated heterostructures, grown on a Si substrate by ultrahigh vacuum chemical vapor deposition, have been investigated. The design is based on a single quantum well active region employing a vertical optical transition, and the observed spectral features are well described by non-equilibrium Green's function calculations. The presence of two peaks highlights a suboptimal injection in the upper state of the radiative transition. Comparison of the electroluminescence spectra with a similar GaAs/AlGaAs structure yields one order of magnitude lower emission efficiency. [ABSTRACT FROM AUTHOR]

The design, modeling, micro-fabrication, and characterization of an ultra-broadband Ge-on-Si waveguide polarization rotator are presented. The polarization rotator is based on the mode evolution approach where adiabatic symmetric and anti-symmetric tapers are utilized to convert from the fundamental transverse magnetic to electric mode. The device is shown to be extremely fabrication tolerant and simple to fabricate. The fabricated devices demonstrate a polarization extinction ratio of ≥15 dB over a 2 μm bandwidth (9–11 μm wavelength) with an average insertion loss of <1 dB, which is an order of magnitude improvement compared to previously demonstrated devices. This device will provide polarization flexibility when integrating quantum cascade lasers on-chip for mid-infrared waveguide molecular spectroscopy. [ABSTRACT FROM AUTHOR]

A 15-item story problem test was written at three readability levels (below grade 4, grades 4-6, above grade 6) by two methods (vocabulary control and sentence control). Six test forms were administered to 1158 children in grades 3-6. Readability level had no effect on problem difficulty. (Author/MNS)

Thermoelectric materials generate electricity from thermal energy using the Seebeck effect to generate a voltage and an electronic current from a temperature difference across the semiconductor. High thermoelectric efficiency ZT requires a semiconductor with high electronic conductivity and low thermal conductivity. Here, we investigate the effect of scattering from threading dislocations of edge character on the thermoelectric performance of individual n and p-channel SiGe multiple quantum well structures. Our detailed physical simulations indicate that while the thermal and electrical conductivities decrease with increasing dislocation scattering/density, the Seebeck coefficient actually increases with increasing threading dislocation density above 106 cm-2 at room temperature, due to an increase in the entropy associated with each carrier. The collective result of these individual effects, is that the present Si-based quantum well designs can tolerate scattering by a threading dislocation density up to ∼108 cm-2, well within the capabilities of modern growth techniques, before significant reductions in ZT due to scattering from threading dislocations is observed. [ABSTRACT FROM AUTHOR]

Thin metal films alone or incorporated in a multilayer stack structure with dielectric films are good candidates of terahertz absorbers necessary for achieving the maximum responsivity in microbolometer devices. However, the design and optimization of these absorber structures depend on the knowledge of the complex refractive index of metal films in the terahertz frequency range, which is not easy to measure or determine from experiment. This paper presents a novel method that allows fast and reliable extraction of the complex refractive index from terahertz time-domain spectroscopy. It starts with terahertz time-domain transmission measurements, followed by Fourier transforms to obtain the transmission spectrum in the frequency range of 0.1–3 THz, and finally an extraction process using the enhanced “on-the-downhill” algorithm. Some experimental examples are given, all of which show good agreement with theoretical calculations. This extraction method, combined with the scattering matrix model, can help design and optimize complicated absorber structures for terahertz microbolometers. [ABSTRACT FROM AUTHOR]

n-type Ge/SiGe terahertz quantum cascade lasers are investigated using non-equilibrium Green's functions calculations. We compare the temperature dependence of the terahertz gain properties with an equivalent GaAs/AlGaAs quantum cascade laser design. In the Ge/SiGe case, the gain is found to be much more robust to temperature increase, enabling operation up to room temperature. The better temperature robustness with respect to III–V is attributed to the much weaker interaction with optical phonons. The effect of lower interface quality is investigated and can be partly overcome by engineering smoother quantum confinement. [ABSTRACT FROM AUTHOR]

Displacement sensors are found in a variety of applications including gravitational wave detectors, precision metrology, tissue imaging, gravimeters, microscopy, and environmental monitoring. Most of these applications benefit from the use of displacement sensors that offer both high precision and stability. This is particularly the case for gravimetry where measurements are often taken over multi-day timescales. In this paper we describe a custom-built microcontroller-based displacement sensor that has been utilized in a micro-electromechanicalsystem gravimeter. The system runs off battery power and is low-cost, portable, and lightweight. Using an optical shadow sensor technique, and by designing a digital lock-in amplier based around a dsPIC33 microcontroller, we demonstrate a displacement sensitivity of 10 nm/Hz down to 300 s, and an rms sensitivity of 1 nm over timescales of one day. The system also provides real time monitoring/control of temperature, using an AD7195 ratiometric bridge to provide mK control of three separate PT100 sensors. Furthermore, a tilt sensor conditioning circuit is incorporated to drive a pair of electrolytic tilt sensors, resulting in the ability to monitor 2 axis tilt at the level of 1 microradian over approximately 1 day. The sensor system described is thus multifunctional and capable of being incorporated into precision accelerometers/gravimeters, or indeed other applications where long term displacement/temperature monitoring is necessary. [ABSTRACT FROM AUTHOR]

This paper presents experimental and simulation analysis of an $\Omega $ -shaped silicon junctionless nanowire field-effect transistor (JL-NWT) with gate lengths of 150 nm and diameter of the Si channel of 8 nm. Our experimental measurements reveal that the ON-currents up to 1.15 mA/ $\mu \text{m}$ for 1.0 V and 2.52 mA/ $\mu \text{m}$ for the 1.8-V gate overdrive with an OFF-current set at 100 nA/ $\mu \text{m}$. Also, the experiment data reveal more than eight orders of magnitude ON-current to OFF-current ratios and an excellent subthreshold slope of 66 mV/dec recorded at room temperature. The obtained experimental current–voltage characteristics are used as a reference point to calibrate the simulations models used in this paper. Our simulation data show good agreement with the experimental results. All simulations are based on drift-diffusion formalism with activated density gradient quantum corrections. Once the simulations methodology is established, the simulations are calibrated to the experimental data. After this, we have performed statistical numerical experiments of a set of 500 different JL-NWTs. Each device has a unique random distribution of the discrete dopants within the silicon body. From those statistical simulations, we extracted important figures of merit, such as OFF-current and ON-current, subthreshold slope, and voltage threshold. The performed statistical analysis, on samples of those 500 JL-NWTs, shows that the mean ${I}_{D} - {V}_{\text {Gs}}$ characteristic is in excellent agreement with the experimental measurements. Moreover, the mean ${I}_{D} - {V}_{\text {Gs}}$ characteristic reproduces better the subthreshold slope data obtained from the experiment in comparison to the continuous model simulation. Finally, performance predictions for the JL transistor with shorter gate lengths and thinner oxide regions are carried out. Among the simulated JL transistors, the configuration with 25-nm gate length and 2-nm oxide thickness shows the most promising characteristics offering scalable designs. [ABSTRACT FROM AUTHOR]

Gravimeters are used to measure density anomalies under the ground. They are applied in many different fields from volcanology to oil and gas exploration, but present commercial systems are costly and massive. A new type of gravity sensor has been developed that utilises the same fabrication methods as those used to make mobile phone accelerometers. In this study, we describe the first results of a field-portable microelectromechanical system (MEMS) gravimeter. The stability of the gravimeter is demonstrated through undertaking a multi-day measurement with a standard deviation of 5.58 × 10-6 ms-2. It is then demonstrated that a change in gravitational acceleration of 4.5 × 10-5 ms-2 can be measured as the device is moved between the top and the bottom of a 20.7 m lift shaft with a signal-to-noise ratio (SNR) of 14.25. Finally, the device is demonstrated to be stable in a more harsh environment: a 4.5 × 10-4 ms-2 gravity variation is measured between the top and bottom of a 275-m hill with an SNR of 15.88. These initial field-tests are an important step towards a chip-sized gravity sensor. [ABSTRACT FROM AUTHOR]

The experimental results from 8 nm diameter silicon nanowire junctionless field-effect transistors with gate lengths of 150 nm are presented that demonstrate on-currents up to 1.15 mA/ $\mu$m for 1.0 V and 2.52 mA/ \mu$m for 1.8 V gate overdrive with an off-current set at 100 nA/\mu$m. On- to off-current ratios above 10^8C. Simulations using drift-diffusion which include density-gradient quantum corrections provide excellent agreement with the experimental results. The simulations demonstrate that the present silicon-dioxide gate dielectric only allows the gate to be scaled to 25 nm length before short-channel effects significantly reduce the performance. If high-K dielectrics replace some parts of the silicon dioxide then the technology can be scaled to at least 10 nm gatelength. [ABSTRACT FROM PUBLISHER]

An aqueous solution method is developed for the facile synthesis of Cl-containing SnSe nanoparticles in 10 g quantities per batch. The particle size and Cl concentration of the nanoparticles can be efficiently tuned as a function of reaction duration. Hot pressing produces n-type Cl-doped SnSe nanostructured compacts with thermoelectric power factors optimized via control of Cl dopant concentration. This approach, combining an energy-efficient solution synthesis with hot pressing, provides a simple, rapid, and low-cost route to high performance n-type SnSe thermoelectric materials. [ABSTRACT FROM AUTHOR]

We address nonradiative recombination pathways by leveraging surface passivation and dislocation management in lm-scale arrays of Ge crystals grown on deeply patterned Si substrates. The time decay photoluminescence (PL) at cryogenic temperatures discloses carrier lifetimes approaching 45 ns in band-gap engineered Ge micro-crystals. This investigation provides compelling information about the competitive interplay between the radiative band-edge transitions and the trapping of carriers by dislocations and free surfaces. Furthermore, an in-depth analysis of the temperature dependence of the PL, combined with capacitance data and finite difference time domain modeling, demonstrates the effectiveness of GeO2 in passivating the surface of Ge and thus in enhancing the room temperature PL emission. [ABSTRACT FROM AUTHOR]

A surfactant-free solution methodology, simply using water as a solvent, has been developed for the straightforward synthesis of single-phase orthorhombic SnSe nanoplates in gram quantities. Individual nanoplates are composed of {100} surfaces with {011} edge facets. Hot-pressed nanostructured compacts ( Eg≈0.85 eV) exhibit excellent electrical conductivity and thermoelectric power factors ( S2 σ) at 550 K. S2 σ values are 8-fold higher than equivalent materials prepared using citric acid as a structure-directing agent, and electrical properties are comparable to the best-performing, extrinsically doped p-type polycrystalline tin selenides. The method offers an energy-efficient, rapid route to p-type SnSe nanostructures. [ABSTRACT FROM AUTHOR]

Transient multiphysics simulations are performed to investigate the thermal and electric performance of a thermoelectric generator (TEG) module placed between hot and cold blocks. Effects of heat radiation, thermal and electric contact on the TEG are examined and the simulated results are compared with experimental data. The predicted temperature difference across the TEG module and the electric voltage and power are in very good agreement with the experimental data. The radiation effect on the thermal and electric performance is negligible and the temperature at the interface of the TEG module substrates is predicted to be non-uniform. The peak temperatures are found in the both ends of the legs, and the maximum Joule heat is generated at the leg ends connected with the hot substrate. [ABSTRACT FROM AUTHOR]

An optimal installation of a compound parabolic concentrator (CCPC) into a scalable solar thermoelectrics and photovoltaics system is desirable by applying analytical tools to improve the optical and thermal performance of a CCPC with a solar cell. In this paper, the optical and thermal performances of an isolated CCPC with solar cell are investigated by employing commercial software 'ANSYS CFX 15.0' with a coupled optical grey and multiphysics model. Numerical results are validated against the experimental data at various incidence angles, especially for the optical concentration ratio and optical efficiency. Results confirm that 'ANSYS CFX' is an effective numerical tool for determining correctly both the optical and thermal behaviour of CCPC. The very important finding is a highest temperature core in the silicon layer of solar cell which may be responsible for a solar cell to work properly. The limitation of the work is that the electric performance of the solar cell is not involved and the simulations are steady. [ABSTRACT FROM AUTHOR]

The design, modeling, fabrication, and characterization of single-photon avalanche diode detectors with an epitaxial Ge absorption region grown directly on Si are presented. At 100 K, a single-photon detection efficiency of 4% at 1310 nm wavelength was measured with a dark count rate of \sim6~megacounts/s, resulting in the lowest reported noise-equivalent power for a Ge-on-Si single-photon avalanche diode detector (1\times 10^-14~WHz^-1/2). The first report of 1550 nm wavelength detection efficiency measurements with such a device is presented. A jitter of 300 ps was measured, and preliminary tests on after-pulsing showed only a small increase (a factor of 2) in the normalized dark count rate when the gating frequency was increased from 1 kHz to 1 MHz. These initial results suggest that optimized devices integrated on Si substrates could potentially provide performance comparable to or better than that of many commercially available discrete technologies. [ABSTRACT FROM AUTHOR]

Si/SiGe and AlGaAs/GaAs resonant tunneling diodes (RTDs) are realized using a self-aligned fabrication process with dimensions ranging from 50 \mu\m down to 30 nm. Using these devices, scaling rules are developed and incorporated into a modified SPICE model. The depletion width and the sidewall current are extracted from the model. The results confirm that the parasitic sidewall current is responsible for the reduction in peak-to-valley current ratio (PVCR) in small-diameter RTDs. A new device layout is demonstrated to significantly reduce the sidewall current for optimum nanoscale performance. Improvements in the PVCRs are demonstrated by this approach. [ABSTRACT FROM AUTHOR]

The development of nanofabrication techniques for creating high aspect ratio (~50:1) sub-10nm silicon nanowires (SiNWs) with smooth, uniform, and straight vertical sidewalls using an inductively coupled plasma (ICP) etching process at 20 °C is reported. In particular, to improve the quality and flexibility of the pattern transfer process for high aspect ratio SiNWs, hydrogen silsesquioxane, a high-resolution, inorganic, negative-tone resist for electron-beam lithography has been used as both the resist for defining sub-10nm patterns and the hard mask for etching the underneath silicon material. The effects of SF6/C4F8 gas flow rates, chamber pressure, platen power and ICP power on the etch rate, selectivity, and sidewall profile are investigated. To minimize plasma-induced sidewall damage, moderate plasma excitation power (ICP power of 600W) and low ion energy (platen power of 6-12W) were used. Using the optimized etch process at room temperature (20°C), the authors have successfully fabricated sub-10nm SiNWs, which have smooth vertical sidewall profile and aspect ratios up to ~50:1. This optimized etch combined with a controlled thermal oxidation allows the realization of consistent, reproducible, and reliable SiNW devices with nominal widths from 100nm down to sub-5nm in silicon on top of SiO2 fabricated on silicon on insulator substrates. [ABSTRACT FROM AUTHOR]

Performance enhancements of up to 170% in drain current, maximum transconductance, and field-effect mobility are presented for nMOSFETs fabricated with strained-Si channels compared with identically processed bulk Si MOSFETs. A novel layer structure comprising Si/Si[sub 0.7]Ge[sub 0.3] on an Si[sub 0.85]Ge[sub 0.15] virtual substrate (VS) offers improved performance advantages and a strain-compensated structure. A high thermal budget process produces devices having excellent on/off-state drain-current characteristics, transconductance, and subthreshold characteristics. The virtual substrate does not require chemical-mechanical polishing and the same performance enhancement is achieved with and without a titanium salicide process. [ABSTRACT FROM AUTHOR]