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This paper describes a four-port MIMO antenna array design featuring bow-tie-shaped slot-loaded patches with wideband capabilities that cover the frequency range from 24.2 GHz to 30.8 GHz. The proposed antenna design is printed on an FR4 substrate and occupies an area of 25 × 24 mm2. The MIMO antenna consists of four antenna arrays that are symmetrically placed in an upper-lower configuration. The bow-tie-shaped slots loaded radiators are separated horizontally by 3.48 mm and vertically by 5.94 mm. Each antenna array contains two elements that are separated by a distance of wavelength/4. The suggested MIMO antenna array delivers a high gain of 19.09 dB at 27.8 GHz and has a bandwidth of 6.6 GHz that covers the frequency band of 24.2–30.8 GHz. The research demonstrates the quality of the proposed MIMO antenna through various diversity parameters such as mutual coupling, port correlation, diversity gain, and data rate that can be transmitted over a communication medium. The simulation results are validated and found to be consistent with the experimental results. The presented antenna covers the entire bandwidth allocated to different regions, including Europe (24.25–27.5 GHz), Sweden (26.5–27.5 GHz), USA (27.5–28.35 GHz), China (24.25–27.5 GHz), Japan (27.5–28.28 GHz), and Korea (26.5–29.5 GHz). The proposed MIMO antenna design could be an excellent option for 26/28 GHz 5G NR n257, n258, and n260 bands under mm-wave wireless communication systems. [ABSTRACT FROM AUTHOR]

In this work, a novel multiple input multiple output (MIMO) array antenna system with a large bandwidth and high gain has been simulated, analyzed, fabricated, and measured. The proposed antenna is structured in 2 × 4 patch configuration along with a cross shaped ground plane loaded with four square and one circular shaped defect. The projected antenna occupies a total size of 4 3. 6 1 1 × 4 3. 6 1 1 × 0. 4 2 mm 3 . Several slots in an elliptic form have been added to the patches to achieve the required results in terms of wide bandwidth and high gain. The MIMO antenna array is fabricated and experimentally tested to confirm the simulation results. The suggested MIMO array antenna offers an impedance bandwidth of 22 GHz covering 22–44 GHz wide range of frequencies with a high peak gain of 17 dBi at 38 GHz. The designed MIMO antenna offers superior diversity performance and it supports several 5G NR bands n257/n258/n259/n260/n261 in the mm-wave spectrum. The suggested MIMO antenna supports 5G application bands that are deployed in UK, USA, China, Europe, Canada, India, and Europe. [ABSTRACT FROM AUTHOR]

A new compact 1 × 4 microstrip patch antenna array design for future 5G applications is presented in this paper. The proposed antenna array consists of square slot loaded with four radiating patch elements. The corporate feed network has been implemented for the excitation of the array. The feed line is connected to the square slot patch through a quarter-wave transformer matching network. The proposed array is designed on an FR-4 substrate with a dielectric constant of 4.4, thickness of 1.6 mm and loss tangent (tan δ) of 0.02. It has a compact dimension of 9.590 × 17.802 × 1. 6 m m 3 . The proposed structure has been designed and simulated by using commercially available HFSS software. The simulated results (reflection coefficient, gain, efficiency, radiation pattern) are verified through the measurement process to confirm the validity of the design concept. The measurement results are in good agreement with the simulated results. The proposed structure resonates at 38.1 GHz with a − 10 dB impedance bandwidth of about 3700 MHz (36.5 GHz to 40.2 GHz). The reflection coefficient at 38.1 GHz is − 34 dB, with a maximum gain of 7.81 dB. The proposed square slot loaded patch antenna array is very promising for 5G communications at 38 GHz band (37–40 GHz). [ABSTRACT FROM AUTHOR]

This paper proposes a low-loss and high-isolation transformer (TF)-based mm-wave single-pole double-throw (SPDT) switch. The center-tapped technique is employed at the secondary coil of TF to improve isolation performance. The TF is implemented with the metals in redistribution layers (RDLs) in integrated fan-out (InFO) wafer level packaging technology to obtain low insertion loss (IL) and small chip size as the TF usually dominates the area of SPDT. The control device of the SPDT is realized in 40 nm bulk CMOS process. The simulated result shows the proposed SPDT achieves a minimum IL of 1.34 dB and the IL is less than 2.2 dB at 24–31 GHz. The isolations are better than 27 dB between two double-throw ports and better than 20 dB between single-pole and double-throw ports, respectively. The proposed SPDT has a compact silicon size of 220 μ m × 1 4 0 μ m (with PADs) and its return losses are better than − 9 dB at 24–31 GHz and. This work explores a new chip-package co-design method for the SPDT and may have some guidance for the co-design of SPDT and antenna in package (AiP). [ABSTRACT FROM AUTHOR]

The feasibility of CMOS circuits operating at frequencies in the upper millimeter wave and low sub-millimeter frequency regions has been demonstrated. A 140-GHz fundamental mode VCO in 90-nm CMOS, a 410-GHz push-push VCO in 45-nm CMOS, and a 180-GHz detector circuit in 130-nm CMOS have been demonstrated. With the continued scaling of MOS transistors, 1-THz CMOS circuits will be possible. Though these results are significant, output power of signal generators must be increased and acceptable noise performance of detectors must be achieved in order to demonstrate the applicability of CMOS for implementing practical terahertz systems. [ABSTRACT FROM AUTHOR]

The range of mm-wave radio communications is severely constrained by high losses arising from the short wavelength and from atmospheric attenuation. Large phased arrays can overcome these limitations, but it is very difficult to realize them using present monolithic beamsteering IC architectures. We propose an alternative architecture for large monolithic phased arrays. The beam is steered in altitude and in azimuth by separately imposing vertical and horizontal phase gradients. This choice reduces IC complexity, making large arrays feasible. Since extensive digital processing provides robust amplitude control and reduces die area, the LOs are processed as digital signals. Being very sensitive to compression, the IF signals are processed as analog signals and distributed by means of synthetic transmission-line buses. With careful frequency planning, this mixed-signal approach can allow large phased arrays to operate at frequencies much higher than those achievable with pure analog design. [ABSTRACT FROM AUTHOR]