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With the aggressive growth of the internet of things-based applications in the domestic and industrial domain, the embedded static memory is also under renovation stage to eliminate classical barriers such as soft errors, poor stability, and mediocre performance. In this work, a novel twelve transistors (12T) SRAM cell is presented that replaces the conventional inverter with Schmitt trigger-based inverter in core latch. The proposed SRAM circuit has been compared with four formerly reported designs for investigating the improvement in terms of various performance metrics. These designs include conventional six transistors (6T), tunable transistor 8T (T8T), PPN inverter-based 10T (PP10T), and stable low read power 11T (S11T) cells. The presented cell effectively minimizes the soft errors attributed to 1. 3 6 × / 1. 2 7 × / 1. 6 6 × / 1. 2 7 × enhancement of critical charge compared to 6T/T8T/PP10T/S11T cells. Also, the proposed bit-cell effectively mitigates multi-bit-cell upsets because it allows bit interleaving array structure. The presented bit-cell also shows reduction in leakage power by 1. 0 8 × / 1. 3 3 × / 0. 4 3 × / 1. 2 8 × in comparison to 6T/T8T/PP10T/S11T cells, respectively. The read and write stability of proposed bit-cell circuit is enhanced by 1. 9 6 × / 1. 8 8 × / 1 × / 1. 9 2 × and 1. 1 5 × / 1. 1 9 × / 1. 2 9 × / 1. 4 5 × , respectively, in comparison to 6T/T8T/PP10T/S11T cells, respectively. In addition to this, proposed cell exhibits improvement in dynamic power, data retention voltage, and overall electrical quality matrix. Variability comparison of key design metrics such as read power and read current of the proposed SRAM circuit with 6T cell has also been presented in this work. [ABSTRACT FROM AUTHOR]

In this paper, a 9T SRAM cell with low power (LP9T) and improved performance has been proposed. This cell is free from half-select issue and works with single-ended read and differential write operation in the sub-threshold region. To evaluate the relative performance, the obtained characteristics of LP9T SRAM cell are compared with other state-of-the-art designs at 45-nm technology node. The read and write power dissipation of LP9T SRAM cell is reduced by 1. 6 5 × and 1. 8 4 × as compared to Conv.6T SRAM cell. In proposed cell, leakage power is reduced by 1. 5 8 × , 1. 4 0 × , 1. 4 7 × , 1. 0 5 × , 1. 5 7 × and 1. 3 1 × as compared to conventional 6T (Conv.6T), low power (LP8T), transmission gate 8T(TG8T), transmission gate 9T (TG9T), Schmitt trigger 9T (ST9T), and positive feedback control 10T (PFC10T) SRAM cells. This reduction in leakage power is attributed to stacking effect. LP9T SRAM cell also exhibits significant improvement in read/write access time as compared to all considered cells. Also, the read and write energy of proposed cell is lowest among all considered cells. The LP9T SRAM cell has 2. 2 × and 1. 6 3 × higher read and write stability as compared to Conv.6T SRAM cell. Proposed SRAM cell has the highest value of ON to OFF current ratio ( I on ∕ I off ) which signifies the highest bit-cell density among all considered cells. The LP9T SRAM cell occupies 1. 2 0 × large area as compared to Conv.6T SRAM cell. The overall quality of SRAM cell is calculated through the electrical quality metric (EQM). It is observed that LP9T SRAM cell has the highest value of EQM in comparison to considered cells at 0.3 V supply voltage. [ABSTRACT FROM AUTHOR]

In the proposed work, a differential write and single-ended read half-select free 12 transistors static random access memory cell is designed and simulated. The proposed cell has a considerable reduction in power dissipation with better stability and moderate performance. This cell operates in subthreshold region and has a higher value of read static noise margin as compared to conventional six transistors static random access memory cell. A power cut-off technique is utilized between access and pull-up transistors during the write operation. It results in an increase in write static noise margin as compared to all considered cells. In the proposed cell, read and write access time is improved along with a reduction in read/write power dissipation as compared to conventional six transistors static random access memory cell. The bitline leakage current in the proposed cell is reduced which improves the Ion/Ioff ratio of the cell under subthreshold region. The proposed cell occupies less area as compared to considered radiationhardened design 12 transistors static random access memory cell. The computed electrical quality metric of proposed cell is better among considered static random access memory cells. Process variation analysis of read stability, access time, power dissipation, read current and leakage current has been performed with the help of Monte Carlo simulation at 3,000 points to get more soundness in the results. All characteristics of static random access memory cells are compared at various supply voltages. [ABSTRACT FROM AUTHOR]

This paper presents a circuit-level technique of designing a low power and half select free 10T Static Random-Access Memory Cell (SRAM). The proposed cell works with single end read operation and differential write operation. The proposed bit-cell is free from half select issue and supports bit interleaving format. The presented 10T cell exhibits 40.75% lower read power consumption in comparison to conventional 6T SRAM cell, attributed to reduction of activity factor during read operation. The loop cutting transistors used in core latch improve write signal-to-noise margin (WSNM) by 14.94% and read decoupled structure improve read signal-to-noise margin (RSNM) by 2. 0 2 × as compared to conventional 6T SRAM. In the proposed work, variability analysis of significant design parameters such as read current, stand-by SNM, and read power of the projected 10T SRAM cell is presented and compared with considered topologies. Mean value of hold static noise margin of the cell for 3000 samples is 1. 7 5 × times higher than the considered D2p11T cell. The proposed 10T cell shows 1. 8 3 × and 1. 2 2 × narrower read access time and write access time, respectively, as compared to conventional 6T SRAM cell. Read current to bit-line leakage current ratio of the proposed 10T cell has been investigated and is improved by 2. 7 5 × as compared to conventional 6T SRAM cell. The write power delay product and read power delay product of the proposed 10T cell are 4. 2 1 × and 2. 7 9 × lower than conventional 6T SRAM cell. In this work, cadence virtuoso tool with Generic Process Design Kit (GPDK) 45 nm technology file has been utilized to carry out simulations. [ABSTRACT FROM AUTHOR]

In this paper, a 11-T static random-access memory (SRAM) cell has been examined that shows a fair reduction in read power dissipation while upholding the stability and moderate performance. In the presented work, parametric variability analysis of various design metrices such as signal to noise margin, read current and read power of the Proposed 11T cell are presented and compared with few considered topologies. The Proposed cell offers single ended write operation and differential read operation. The improvement in read signal to noise margin and write signal to noise margin with respect to conventional 6T SRAM is 10.63% and 33.09%, respectively even when the write operation is single ended. Mean hold static noise margin of the cell for 3000 samples is 1. 7 5 × times higher than considered D2p11T cell. Sensitivity analysis of data retention voltage (DRV) with respect to temperature variations is also investigated and compared with considered topologies. DRV variation with temperature is least in FF process corner. In comparison to conventional 6T SRAM cell, the write and read delay of Proposed 11T cell gets improved by 2. 5 5 × and 1.64%, respectively. Proposed 11T topology consumes least read energy in comparison with considered topologies. In comparison with another considered 11T topology, i.e., D2p11T cell, Proposed cell consumes 13.11% lesser area. Process variation tolerance with Monte Carlo simulation for read current and read power has been investigated using Cadence virtuoso tool with GPDK 45-nm technology. [ABSTRACT FROM AUTHOR]