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Today's desktop rendering platforms typically use GPUs, which have become the most powerful computing chip to meet the growing visual needs, especially in ray tracing. However, ray tracing is challenging for mobile platforms because mobile GPUs need to accommodate insufficient computing power, hardware resources, and memory bandwidth. This paper presents a novel architecture for the mobile domain called Mobile Multiple stacks Ray Tracing (MMsRT). The most complicated calculations in ray tracing are completed through lightweight embedded design. MMsRT has three key features: First, we set multiple stacks to ensure multiple rays are parallel in the system. Second, it sets a stack cache to store the data in stacks when the storage space of multiple stacks is insufficient. Third, we adopt the data prefetching mechanism to set caches to improve the cache hit rate and performance. An accurate simulator test proves that our design can be applied to mobile devices. We calculate the performance of about 82.9 Million Rays Per Second (MRPS), the chip area is about 0.856 mm2, and 96.85 MRPS/mm2. [ABSTRACT FROM AUTHOR]

Hardware prefetching has always been a crucial mechanism to improve processor performance. However, an efficient prefetch operation requires a guarantee of high prefetch accuracy; otherwise, it may degrade system performance. Prior studies propose an adaptive priority controlling method to make better use of prefetch accesses, which improves performance in two-level cache systems. However, this method does not perform well in a more complex memory hierarchy, such as a three-level cache system. Thus, it is still necessary to explore the efficiency of prefetch, in particular, in complex hierarchical memory systems. In this paper, we propose a composite hierarchy-aware method called CHAM, which works at the middle level cache (MLC). By using prefetch accuracy as an evaluation criterion, CHAM improves the efficiency of prefetch accesses based on (1) a dynamic adaptive prefetch control mechanism to schedule the priority and data transfer of prefetch accesses across the cache hierarchical levels in the runtime and (2) a prefetch efficiency-oriented hybrid cache replacement policy to select the most suitable policy. To demonstrate its effectiveness, we have performed extensive experiments on 28 benchmarks from SPEC CPU2006 and two benchmarks from BioBench. Compared with a similar adaptive method, CHAM improves the MLC demand hit rate by 9.2% and an improvement of 1.4% in system performance on average in a single-core system. On a 4-core system, CHAM improves the demand hit rate by 33.06% and improves system performance by 10.1% on average. [ABSTRACT FROM AUTHOR]

Multicore designs have become the dominant organization for future high performance microprocessors. Instead of increasing cache sizes, clock frequencies, pipeline depths or register file (RF) ports, multicore designs tend to make each processor core simple but highly efficient. This new dimension for improving performance and power efficiency in multicore requires us to rethink processor architecture. Multiply-accumulate (MAC) operation is such a performance improvement technique that needs to be reviewed. MAC operation is the fundamentals of many DSP and multimedia applications, but it tends to be awkward to implement in an orthogonal instruction set architecture (ISA) because of operand bandwidth problem, instruction encoding problem, and hardware cost problem. So a big question is that whether we should support MAC or not in high-efficiency processor designs? This paper does a comparative study on this question and introduce data bandwidth relaxing techniques to eliminate narrow bandwidth provided by two-port RFs. The trade-off are also made to solve the instruction coding and hardware cost problem. So, the new design wisdom becomes that if you support multiply (MUL) operation, then support MAC operation. [ABSTRACT FROM AUTHOR]