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Three-Dimensional (3D) Integrated Circuits (ICs) offers integrating capabilities of 'More than Moore' while overcoming CMOS scaling limitations, providing the advantages of low power, high performance and reduced costs. The design of the Clock Distribution Network (CDN) for a 3D IC has to be done meticulously to guarantee reliable operation. In the design of the CDN, clock buffers are crucial units that affect the clock skew, slew and power dissipated by the clock tree. In this paper, we propose a two-stage buffering technique that inserts clock buffers for slew control and skew minimization. Such a buffering technique decreases the number of buffers and power dissipated in the clock tree when compared to previous works which were inserting buffers primarily for slew control. We incorporate the proposed buffering technique into the 3D clock tree synthesis algorithm of previous work and evaluate the performance of the clock tree for both single Through-Silicon Vias (TSV) and mutiple TSV approach. When evaluated on IBM benchmarks (r1-r5), our buffering technique results in 25-28% reduction in buffer count and 25-29% reduction in power for single TSV-based 3D CDN. For multi-TSV approach, the performance of our work is even better:around 31-38% reduction in buffer count and 32-39% reduction in power. [ABSTRACT FROM AUTHOR]

While copper interconnect scaling is approaching its fundamental physical limit, increasing wire resistivity and delay have greatly limited the circuit miniaturization. The emerging carbon nanotube (CNT) interconnects, especially single-walled CNTs (SWCNTs) bundle interconnects, have become a promising replacement material. Nevertheless, physical design optimization techniques are still needed to allow them achieving the desired performances. While the preliminary conference version of this work [L. Liu, Y. Zhou and S. Hu, Proc. IEEE Computer Society Annual Symp. on VLSI (ISVLSI), 2014] designs the first timing driven buffer insertion technique for SWCNT interconnects, it only considers resistive and capacitive effects but not inductive effects. Although inductance could be negligible for prevailing CNT-based circuit designs, it becomes important when designing ultra-high performance chips in the future. Thus, this paper considers buffering inductive bundled SWCNTs interconnects through developing a dynamic programming algorithm for buffer insertion using the RLC tree delay model. Our experiments demonstrate that bundled SWCNTs interconnect-based buffering can effectively reduce the delay by over when inductive effects are considered. With the same timing constraint, bundled SWCNTs interconnect-based buffering can save over 20% buffer area compared to copper interconnect based buffering, while still running about faster. [ABSTRACT FROM AUTHOR]

This paper proposes a method of buffering instructions by software-based prefetching. The method allows low-end processors to improve their instruction throughput with a minimum of additional logic and power consumption. Low-end embedded processors do not employ caches for mainly two reasons. The first reason is that the overhead of cache implementation in terms of energy and area is considerable. The second reason is that, because a cache's performance primarily depends on the number of hits, an increasing number of misses could cause a processor to remain in stall mode for a longer duration. As a result, a cache may become more of a liability than an advantage. In contrast, the benchmarked results for the proposed software-based prefetch buffering without a cache show a 5-10% improvement in execution time. They also show a 4% or more reduction in the energy-delay-square-product (ED2P) with a maximum reduction of 40%. The results additionally demonstrate that the performance and efficiency of the proposed architecture scales with the number of multicycle instructions. The benchmarked routines tested to arrive at these results are widely deployed components of embedded applications. [ABSTRACT FROM AUTHOR]

The aim of this paper is to deal with a simulation study on effect of part launching, part sequencing at central buffer and tool selection rules on a flexible manufacturing system (FMS) involving tool movement along with part movement policy. A typical FMS is selected for a study of discrete event simulation model. Simulation experiments are conducted on various combinations of decision rules and it is found to be good in evaluated performance measures. [ABSTRACT FROM AUTHOR]

Quality of service (QoS) for internet traffic management requires good traffic models and good estimation of sharing network resource. A link of a network processes all traffic and it is designed with certain capacity C and buffer size B. A Generalized Markov Fluid model (GMFM), introduced by Marrón (2012), is assumed for the sources because it describes in a versatile way the traffic, allows estimation based on traffic traces, and also consistent effective bandwidth (EB) estimation can be done. QoS, interpreted as buffer overflow probability, can be estimated for GMFM through the EB estimation and solving the optimization problem presented in Courcoubetis and Siris [ Perform. Eval. 48:5-23, 2002], the so-called inf-sup formulas. In this work, we implement a code to solve the inf-sup problem and other optimization related with it, that allow us to do traffic engineering in links of data networks to calculate both, minimum capacity required when QoS and buffer size are given or minimum buffer size required when QoS and capacity are given. [ABSTRACT FROM AUTHOR]

As networks-on-chips (NoCs) are expected to provide the necessary scalable communication medium for future many-core systems-on-chips (SoCs) optimizing their resources is of great importance. What is really needed is an efficient NoC architecture with optimized resources that requires very little customization by the SoC developers. One of the most important area and power hungry resources is the NoC's buffers. In this work, a new Modified Fat Tree (MFT) NoC architecture with buffers engineered for maximum efficiency (performance versus area) is presented. Extensive simulations are used to show optimum buffer design/placement under different conditions of traffic types and NoC sizes. [ABSTRACT FROM AUTHOR]

In this paper we study an online minimum makespan scheduling problem with a reordering buffer. We obtain the following results: (i) for m > 51 identical machines, we give a 1.5-competitive online algorithm with a buffer of size ⌈1.5m⌉; (ii) for three identical machines, we give an optimal online algorithm with a buffer size six, better than the previous nine; (iii) for m uniform machines, using a buffer of size m, we improve the competitive ratio from 2 + ε to 2 − 1/m+ ε, where ε > 0 is sufficiently small and m is a constant. [ABSTRACT FROM AUTHOR]

High-radix router based on the tile structure requires large amount of buffer resources. To reduce the buffer space requirement without degrading the throughput of the router, shared buffer management schemes like dynamically allocated multi-queue (DAMQ) can be used by improving the buffer utilization. Unfortunately, it is commonly regarded that DAMQ is slow in write and read. To address this issue, we propose a fast and fair DAMQ structure called F2DAMQ for high-radix routers in this paper. It uses a fast FIFO structure in the implementation of idle address list as well as data buffer and achieves some critical performance improvement such as continuous and concurrent write and read with zero-delay. Besides, F2DAMQ also uses a novel credit management mechanism which is efficient in avoiding one virtual channel (VC) monopolizing the shared part of the buffer and achieving fairness among competing VCs sharing the buffer. The analyses and simulations show that F2DAMQ perforins well in achieving low latency, high throughput and good fairness under different traffic patterns. [ABSTRACT FROM AUTHOR]

In system level design or architecture design stage of SoCs, it is important to estimate the system parameters such as bus utilization and buffer capacity. A novel bus modeling method which was derived from Markov model for obtaining these parameters of an on-chip-bus system has been proposed in this paper. This modeling approach employs Markov chain to describe the state change of the system. This method was used in architecture design verification of a video format converting (VFC) chip. By comparing the simulation result and the pessimistic estimate value, the rationality and high efficiency of this method were verified, and more than 55% of FIFOs size are saved. It is suitable for analyzing various bus systems, such as user-defined buses, industrial standard buses, multi-core and multi-bus systems. [ABSTRACT FROM AUTHOR]

In a large multiprocessor server platform using multicore chips, the scheduler often migrates a thread or process, in order to achieve better load balancing or ensure fairness among competing scheduling entities. Each migration incurs a severe performance impact from the loss of cache and Translation Lookaside Buffer (TLB) footprints and subsequent higher cache misses and page walks. Such impact is likely to be more severe in virtualized environments, where high over-subscription of CPUs is very common for server consolidation workloads or virtual desktop infrastructure deployment, causing frequent migrations and context switches. We demonstrate the performance benefit of preserving a portion of L2 cache-in particular, MRU cache lines-and warming the destination L2 cache by prefetching those cache lines under different migration scenarios. We observed a 1.5-27% reduction in CPI (cycles per instruction) following a migration. We also study the effectiveness of preserving TLB entries over a context switch or migration. [ABSTRACT FROM AUTHOR]

A wide loop bandwidth in fractional-N PLL is desirable for good jitter performance. However, a wider bandwidth reduces the effective oversampling ratio between update rate and loop bandwidth, making quantization error a much bigger noise contributor. A successful implementation of a wideband frequency synthesizer is in managing jitter and spurious performance. In this paper we present a new PLL architecture for bandwidth extension. By using clock squaring buffers with built-in offsets, multiple clock edges are extracted from a single reference cycle and utilized for phase update, thereby effectively forming a reference multiplier. This enables a higher oversampling ratio for better quantization noise shaping and makes a wideband fractional-N PLL possible. [ABSTRACT FROM AUTHOR]

Dual instruction execution (DIE) is an effective instruction-level temporal redundancy technique to improve the datapath reliability against transient errors for superscalar microprocessors. However, previous study shows that the performance overhead of dual instruction execution on an out-of-order core is substantial, primarily due to the serious resource contention problems such as the ALU bandwidth. In this paper, we propose a novel approach to reducing the performance overhead of DIE without compromising the datapath reliability. In the proposed scheme, both the primary and the duplicate instructions of DIE can exploit the ECC-protected instruction reuse buffer (IRB) for mitigating the resource contention of DIE by minimizing the number of dynamic instructions executed, leading to better performance without impacting the reliability of DIE. Our experiments indicate that the proposed approach can reduce the performance loss of dual instruction execution by up to 70.8%, with 51.1% on average, and can reduce the performance loss of DIE-IRB by up to 17.2%, with 7.1% on average, while providing reliability comparable to DIE or DIE-IRB. [ABSTRACT FROM AUTHOR]

The present paper addresses an improved low-power high-speed buffer amplifier topology for large-size liquid crystal display applications. The proposed buffer achieves high-speed driving performance while drawing a low quiescent current during static operation. The circuit offers enhanced slewing capabilities with a limited power consumption by exploiting a slew detector which monitors the output voltage of the input differential amplifier and outputs an additional current signal providing slew-rate enhancement at the output stage. Post-layout simulations show that the proposed buffer can drive a 1 nF column line load with 8.5 V/μs slew-rate and 0.8 μs settling time, while drawing only 8 μA static current from a 3 V power supply. [ABSTRACT FROM AUTHOR]

This study addresses a two-stage flowshop with a batch machine in stage 1 and a discrete machine in stage 2, subject to the constraint that the input buffer of the discrete machine can only host limited number of jobs. The batch machine processes a batch of jobs simultaneously, and the discrete machine processes one job at a time. The objective function of the problem is the makespan minimization. Several properties are proposed to solve the special case of the problem optimally. An effective heuristic is presented, and a branch-and-bound procedure is proposed for benchmarking. Extensive experimentation shows that the heuristic yields good results. [ABSTRACT FROM AUTHOR]

A transconductance operational amplifier specifically optimized for a switched-capacitor LCD column driver is presented. It exploits MOS transistors in subthreshold region and dissipates 670 nA at DC. Despite this extremely low quiescent current value, the amplifier exhibits a DC gain of about 80 dB, and a gain-bandwidth product and phase margin around 2 MHz and 70°, with a load capacitance of 500 fF. Besides, working in class AB, the solution provides a slew rate equal to 27 V/μs. With exception of the DC gain, these performances represent an improvement with respect to comparable solutions, and are obtained while halving the area occupation. [ABSTRACT FROM AUTHOR]

We consider here reduction of send latencies for send-and-forget type communications, where senders do not reuse data that have already been sent. We introduce a commit based message sending approach, and describe the corresponding application programming interfaces. These interfaces allow applications to take advantage of message buffering, such as overlapping of computations and communications, while avoiding performance degradation due to intermediate memory copy. The approach works by allowing applications to safely access the implementation buffer through the provided interfaces. Experimental results show that the new approach is effective, and reduces the interface latency significantly compared to related approaches. Since send-and-forget type communications are often observed in skeletal programming, we demonstrate the approach by implementing a pipeline algorithmic skeleton. [ABSTRACT FROM AUTHOR]

A translation lookaside buffer (TLB) is a high-speed associative cache of recently used virtual-to-physical address translations. The operating system can deal with a TLB miss through software trap handling. A possible technique for such software trap handling uses translation storage buffers (TSBs). A TSB is an operating system data structure that caches the most recent address translations. On a TLB miss, the TLB trap handler searches the TSB for the missing address translation. If the search generates a hit, the address mapping is added to the TLB. In current implementations, TSBs are organized in a variety of ways: a global TSB for all CPUs within the system, a per-processor TSB, or a per-process TSB. All of the aforementioned techniques have various limitations that will be addressed in this paper. In this work, we propose a new framework for TSBs generation and allocation. In the proposed approach, a policy of resizing and dynamically allocating TSBs for the different processes is used. This dynamic policy allows the system to adopt to different workloads while achieving a low TSB context invalidation overhead. In addition, with the ability to assign a separate TSB to each process, thrashing is practically eliminated. Implementation and experimental results of the proposed scheme are reported. Comparisons against existing implementations confirmed the expected performance enhancement. [ABSTRACT FROM AUTHOR]

Communication in parallel applications is a combination of data transfers internally at a source or destination and across the network. Previous research focused on quantifying network transfer costs has indirectly resulted in reduced overall communication cost. Optimized data transfer from source memory to the network interface has received less attention. In shared memory systems, such memory-to-memory transfers dominate communication cost. In distributed memory systems, memory-to-network interface transfers grow in significance as processor and network speeds increase at faster rates than memory latency speeds. Our objective is to minimize the cost of internal data transfers. The following examples illustrating the impact of memory transfers on communication, we present a methodology for classifying the effects of data size and data distribution on hardware, middleware, and application software performance. This cost is quantified using hardware counter event measurements on the SGI Origin 2000. For the SGI O2K, we empirically identify the cost caused by just copying data from one buffer to another and the middleware overhead. We use MPICH in our experiments, but our techniques are generally applicable to any communication implementation. [ABSTRACT FROM AUTHOR]

In this paper, we propose an architecture level analysis of the frame buffer access pattern of the recent 3D graphics accelerators that utilize multiple pipelined rendering engines. Based on this analysis, we propose an energy efficient memory address converter for an SoC-based 3D graphics system with an SDRAM frame buffer. About 30% of energy reduction and 20% of runtime reduction is obtained with the address converter. With dynamic power management feature of SDRAM, the energy gains increase to about 50%. The energy and runtime gains are generated by an access pattern analysis based division and assignment of frame buffer onto multiple memory modules. With this proposed access pattern analysis, a frame buffer system optimization of an IP-based 3D graphics accelerator can be performed at early architecture design level. [ABSTRACT FROM AUTHOR]

We consider a communication model in which the intermediate nodes cannot store in-transit messages. Under this communication model we study the all-node multicast operation on multidimensional grids and tori. We derive optimal algorithms that are compactly described using a short sequence of node identities. This characteristic contributes to the simplicity of the router, the unit that resides at each processor and is dedicated to handle communication. [ABSTRACT FROM AUTHOR]