Search

Hall electron mobility in buried QW InGaAs channels, grown on InP substrates with HfO 2 gate oxide, is analyzed experimentally and theoretically as a function of top barrier thickness and composition, carrier density, and temperature. Temperature slope α in μ ~Tα dependence is changing from α=-1.1 to +1 with the reduction of the top barrier thickness indicating the dominant role of remote Coulomb scattering (RCS) in interface-related contribution to mobility degradation. Insertion of low-k SiO x interface layer formed by oxidation of thin in-situ MBE grown amorphous Si passivation layer has been found to improve the channel mobility, but at the expense of increased EOT. This mobility improvement is also consistent with dominant role of RCS. We were able to a obtain a reasonable match between experiment and simple theory of the RCS assuming the density of charges at the high-k/barrier interface to be in the range of (2-4)×1013 cm-2.

An overview of III-V MOSFET technological challenges in comparison to well-established heterostructure-based FET technologies is presented with an emphasis on required properties and possible solutions. Possible approaches to achieve thermodynamically stable high- k gate stack with low interface trap density are reviewed, followed with our results on amorphous Si interface passivation layer (IPL) in-situ deposited on top of GaAs or strained InGaAs MOSFET channels grown by molecular beam epitaxy. Main issues of Si IPL, namely increased equivalent oxide thickness due to IPL oxidation and Si diffusion into the semiconductor channel, are addressed using an in-situ deposited HfO 2 with ultrathin (down to 0.25 nm) Si IPL and controlling its bonding state at the interface. Enhancement mode inversion-type MOSFET with HfO 2 high- k oxide is demonstrated. The device employs amorphous Si interface passivation layer, sputter-deposited high- k oxide and metal TaN gate and modulation p-doped GaAs / AlGaAs heterostructure with inversion n -channel formed at the interface with the oxide. The MOSFET with equivalent oxide thickness of 3.7 nm and long 100 μm channel have maximum DC transonductance of 0.9 mS/mm, Ion/Ioff = 2×104 (at low Ioff of 30 nA) and effective channel mobility exceeding 1000 cm2/V-s at sheet electron density 12 cm-2.

Alternative channel materials with superior transport properties over conventional silicon based systems are required for supply voltage scaling in CMOS circuits. Group III- Sb 's are a candidate for high mobility p-channel applications due to a low hole effective mass, large injection velocity in scaled devices and the ability to achieve enhanced hole mobility in strained quantum wells (QW). Multiple challenges in antimonide MOSFET development are assessed and developed technologies were implemented into p-channel MOSFET fabrication with a low thermal processing budget of 350°C. These challenges include growth of “bulk” GaSb and bi-axial compressively strained In x Ga 1-x Sb QW channels on lattice mismatched GaAs substrates, reduction of interface trap state density (Dit) at the III- Sb /high-k oxide interface and avoiding ion implanted source and drain contacts with high temperature activation annealing. A “self-aligned” single mask p-channel MOSFET fabrication process was developed on buried In 0.36 Ga 0.64 Sb QW channels using intermetallic source and drain contacts. The first “gate-last” MOSFET process on In 0.36 Ga 0.64 Sb QW channels with pre-grown epitaxial p++- GaSb contacts is demonstrated. InAs has been proven to be an excellent etch stop layer when using an optimized tetramethylammonium hydroxide (TMAH) etch of p++- GaSb to prevent InGaSb QW damage.