1. An Efficient and High-Speed Implementation of QRD-MGS Algorithm for STAP Application Based on Floating Point FPGAs
- Author
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Ghafar Darvish, Narjes Hasanikhah, Siavash Amin-Nejad, and M. R. Moniri
- Subjects
020301 aerospace & aeronautics ,Floating point ,Computer science ,020206 networking & telecommunications ,02 engineering and technology ,General Medicine ,Interference (wave propagation) ,QR decomposition ,Space-time adaptive processing ,0203 mechanical engineering ,Hardware and Architecture ,0202 electrical engineering, electronic engineering, information engineering ,Clutter ,Electrical and Electronic Engineering ,Field-programmable gate array ,Algorithm ,Linear equation - Abstract
Space-Time Adaptive Processing (STAP) can harness the efficacy of interference and clutter significantly. Calculations of the STAP weights involve solving linear equations which require very intensive computations. In this paper, the QR decomposition (QRD) using the modified gram-schmidt (MGS) algorithm is parameterized with vector size to create a trade-off between the hardware resources utilization and computation time. To achieve an efficient floating point structure, the proposed architecture of QRD-MGS algorithm is simulated and implemented in two modes: single-vector and multi-vector. Results show that the multi-vector method can lead to a high-performance design with higher operating frequency, lower power consumption, and less resource utilization than the single-vector method. For example, Modelism simulations show that the decomposition of a [Formula: see text] matrix with vector size of 17 takes 7.86[Formula: see text][Formula: see text]s with the maximum clock frequency of 282[Formula: see text]MHz, for implementation on the Arria10 FPGA. In real STAP applications, the matrix sizes are too large to be fit on FPGAs and the update rate of the weights are high. Therefore, this method can fit any matrix in the contemporary FPGAs with an acceptable update rate.
- Published
- 2019
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