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Electrocatalytic hydrogen evolution reaction (HER) is regarded as a sustainable and green way for H2 generation, which faces a great challenge in designing highly active, stable electrocatalysts to replace the state‐of‐art noble metal‐platinum catalysts. 1T MoS2 is highly promising in this regard, but the synthesis and stability of this is a particularly pressing task. Here, a phase engineering strategy has been proposed to achieve a stable, high‐percentage (88%) 1T MoS2/chlorophyll‐a hetero‐nanostructure, through a photo‐induced donation of anti‐bonding electrons from chlorophyll‐a (CHL‐a) highest occupied molecular orbital to 2H MoS2 lowest unoccupied molecular orbital. The resultant catalyst has abundant binding sites provided by the coordination of magnesium atom in the CHL‐a macro‐cycle, featuring higher binding strength and low Gibbs‐free energy. This metal‐free heterostructure exhibits excellent stability via band renormalization of Mo 4d orbital which creates the pseudogap‐like structure by lifting the degeneracy of projected density of state with 4S in 1T MoS2. It shows extremely low overpotential, toward the acidic HER (68 mV at the current density of 10 mA cm−2), very close to the Pt/C catalyst (53 mV). The high electrochemical‐surface‐area and electrochemical turnover frequency support enhanced active sites along with near zero Gibbs free energy. Such a surface‐reconstruction strategy provides a new avenue toward the production of efficient non‐noble‐metal‐catalysts for the HER with the aim of green‐hydrogen production. [ABSTRACT FROM AUTHOR]

This paper presents power and area optimized, high‐speed metal‐oxide‐semiconductor (MOS) current mode logic (MCML)‐based frequency dividers. Each differential pair in the divider is sized separately to minimize the overall power consumption. The divide‐by‐2 frequency divider has been realized in a 180‐nm complementary MOS (CMOS) process technology, and postlayout simulation results show that the proposed frequency divider can work up to an operating frequency of 18.8 GHz in the worst‐case process corner with a maximum power dissipation of 1.715 mW under 1.8‐V supply. It gives a bandwidth of 19.9 GHz which ranges from 1 to 20.9 GHz. The divider occupies a 0.106 × 0.09 mm2 area. The performance corresponds to the figure of merit (FoM) of 43.61 dB. The same optimized latches and two EX‐OR gates are used to design a divide‐by‐5 frequency divider that is also realized in 180‐nm CMOS process technology. The postlayout simulation results show that the proposed divide‐by‐5 frequency divider can faithfully work up to an operating frequency of 12.12 GHz in worst‐case process corner with an excellent power head performance. The maximum power dissipation of the core circuit is 1.39 mW under 1.8‐V supply. It occupies a 0.166 × 0.116 mm2 area. The performance corresponds to the FoM of 26.56 dB which compares favorably with the state of the art. [ABSTRACT FROM AUTHOR]

In this study, a multiphase fractional phase‐locked loop (PLL) is presented with methods to reduce spurs. General causes of spurs are non‐idealities of the phase‐frequency detector (PFD) and charge pump (CP) and phase errors between the adjacent phases from the oscillator. In the architecture, the non‐idealities of the PFD and CP are compensated and a phase correction circuit is added after the oscillator phase generator to reduce the phase errors, and hence minimise the spurs. Spurs may still be persistent after these modifications due to process variations and device mismatch. The effect is visible in the perturbations of the loop filter control voltage. The residual spurs are minimised by further filtering the control voltage using a moving average filter and then applying it to the oscillator. The PLL is designed in 180 nm technology and outputs a 400 MHz carrier. The highest fractional spur is decreased from −36 to −66 dBc through phase correction and control voltage filtering. [ABSTRACT FROM AUTHOR]

This paper proposes a new spur reducing architecture of phase-locked loop-based frequency synthesizer. With an array of switched capacitors and a delay locked loop, the charge coming from its charge pump is evenly transferred to its loop filter at a fixed number of equi-spaced time intervals. It results in the reduction of fundamental and higher-order harmonics of the reference spur. The proposed architecture has been designed and fabricated in 180 nm CMOS technology. Randomization scheme has also been incorporated in the proposed architecture to reduce the effect of implementation mismatch on the output spur. Measured result shows about 5.47 dB reduction of fundamental spur compared to that of the conventional architecture with almost no degradation of noise performance. [ABSTRACT FROM AUTHOR]

This paper reports an analytical approach to predict the reference spur of a conventional frequency synthesiser more accurately in comparison with the existing technique where the ripple voltage waveform at voltage controlled oscillator input is approximated by narrow rectangular pulse. In this work, the ripple voltage waveform is represented by a combination of triangular and rectangular pulses. Transistor level SPICE simulations show that using the proposed approach, the error in the predicted spur has been reduced from about 29.84 to 0.64 dB. Measured result shows 4.39 dB error in the predicted spur. The derived expression has been extended further to predict the spur in frequency synthesisers having pulse repetition‐based spur reducing technique including the repetition mismatch. [ABSTRACT FROM AUTHOR]

This study presents a new spur reducing architecture of phase‐locked loop‐based frequency synthesiser. In the proposed architecture, an array of switched capacitors and a delay locked loop are used to evenly transfer the charge, coming from its charge pump, to its loop filter at a fixed number of equi‐spaced time intervals. It reduces fundamental as well as higher‐order harmonics of the reference spur. The proposed architecture has been designed and fabricated using 180 nm complementary metal oxide semiconductor technology. Measured result shows about 17.64 dB reduction of the fundamental spur compared with that of the conventional architecture. [ABSTRACT FROM AUTHOR]