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In this study, a polyhedral approximation method for reachable sets of linear delay systems is investigated. For a continuous linear system with multiple delays, the first Euler scheme combining with linear interpolation is used to transform it into a discrete one. Then a polyhedral approximation method based on optimisation techniques is proposed to compute the discrete reachable set. By specifying an approximation error and solving a finite number of convex optimisation problems, a polyhedron can be constructed as the approximation of the discrete reachable set. The approximation quality measured in Hausdorff distance can be directly controlled. Next, illustrated examples are given to demonstrate the effectiveness of the proposed method. Finally, the authors show some reachable sets of linear delay control systems, and they compare the proposed method with some other methods in the literature. Numerical results clearly show the superior performance of the proposed method. [ABSTRACT FROM AUTHOR]

Bird's eye view (BEV) generation from front‐looking video stream is considered an important pre‐processing task in various computer vision applications such as driver assistance systems. In this work, hardware implementation of this process using high‐level synthesis in Simulink environment has been considered for rapid prototyping under real‐time constraints. Traditionally, researchers have employed lookup table‐based approaches to circumvent the exorbitant cost of implementing arithmetic modules associated with the perspective transformation. The hardware implementation scheme proposed here, however, demonstrates that a polynomial approximation over the limited domain of the involved operands not only saves precious hardware resources but also provides better fixed‐point precision. Synthesis results on Zynq‐7000 FPGA show that the proposed circuit reduces the block memory utilisation by 9% compared to the lookup table‐based built‐in Simulink Vision HDL block. The proposed design evaluates the results in fixed‐point format which is essential for subsequent bilinear interpolation to produce high‐fidelity output frame, albeit at the cost of 4% increase in DSP48E utilisation. The approximation error of the proposed solution is less than quarter‐pixel on average. The proposed hardware has been integrated as an IP core in a hardware‐software co‐design system. The whole framework is publicly available to facilitate practitioners and researchers. [ABSTRACT FROM AUTHOR]