1. Architectural Design Issues in a Clockless 32 Bit Processor Using an Asynchronous HDL
- Author
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Young-Woo Kim, Myeong-Hoon Oh, Sanghoon Kwak, Sung-Nam Kim, and Chi-Hoon Shin
- Subjects
Synchronous circuit ,Asynchronous system ,General Computer Science ,Computer science ,business.industry ,Timing closure ,32-bit ,Electronic, Optical and Magnetic Materials ,Microarchitecture ,Synchronizer ,Asynchronous communication ,Embedded system ,Electrical and Electronic Engineering ,business ,Asynchronous circuit - Abstract
As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a largescale asynchronous circuit, we design a fully clockless 32-bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top-down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre-layout simulation utilizing 0.13-μm CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 µW/MHz and is comparable to that of a synchronous counterpart.
- Published
- 2013
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