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Due to the electronic and structural properties of silicon, silicon nanowires have a great potential in nanoscale electronic devices and sensors. Silicon nanowires used for reconfigurable field effect transistors are designed, synthesized and characterized after each step in order to ensure excellent electrical and physical properties of the end product and to study various process parameters. In this study, silicon nanowire based reconfigurable field effect transistors are studied as as-grown “forests”, individually, oxidized and after forming Schottky junctions. The analysis is performed using scanning electron microscopy and transmission electron microscopy. Focused ion beam based preparation was carried out in the case of samples with Schottky junctions. This paper provides a comprehensive description of sample preparation and characterization of the nanowires.

Continuous scaling of Cu interconnect structures can significantly impact reliability-limiting processes such as electromigration and stress-induced voiding. Prior to the 65 nm technology node, mass transport under electromigration is dominated by diffusion along the Cu/dielectric cap interface and the electromigration lifetime will degrade by about half for every generation, even with the same current density. Beyond the 65 nm node, small grains were found to mix with bamboo grains in the 90 nm Cu damascene lines and the contribution of the grain boundary transport degraded the electromigration lifetime. The scaling effects on microstructure and electromigration reliability are examined in this paper with the objective of identifying the key issues and exploring potential solutions for sub-100 nm Cu interconnects. We discuss first the scaling effect on electromigration lifetime and the effect due to the small grains on electromigration lifetime and statistics. This is followed by a discussion on grain growth studies focusing on the formation of small grains and a recent simulation study on small grain effect on electromigration reliability. This paper concludes with a discussion of some recent developments in analytical techniques to investigate grain structure and electromigration reliability in sub-100 nm Cu lines.

A review. Research and development in the field of future functional materials for electronics and photonics require the competences from several areas of science and engineering such as material synthesis, nanotechnol., nanoanal., physics, chem., biol., and elec. and mech engineering.

The characterization of nanoscale regions in present and future device structures of leading-edge microelectronic products requires probes with dedicated features tailored on the nanoscale. SPM tips are used not only for conventional AFM characterization, but also for electrical, thermal and optical investigation of devices. For particular applications as nano-Raman spectroscopy or conductive AFM, highly reproducible metal tips or metallized tips are needed. In this paper, new approaches to tailor those tips using the FIB technique, and to characterize the tips using dedicated structures and adapted AFM methods are described. Based on a numerical procedure, the tip quality is described quantitatively. The described preparation and calibration techniques offer new possibilities for the routine application of nanostructures and nanodevices as needed for advanced SPM techniques and nanosensors.

Both in situ microscopy experiments at embedded inlaid copper interconnect structures and numerical simulations based on a physical model provide information about electromigration-induced degradation mechanisms in on-chip interconnects. It is shown that the modification of the bonding strength of the weakest interface results in completely changed degradation and failure mechanisms. Transmission electron microscopy (TEM) images of standard Cu/SiNx interfaces are compared with strengthened interfaces, e. g., after applying an additional metal coating or a self-assembled monolayer (SAM) on top of the polished copper lines. The changed degradation mechanisms as observed with the in situ scanning electron microscopy (SEM) experiment and as predicted based on the numerical simulations are explained based on TEM images.

In-situ SEM and XRM studies of fully embedded via/line interconnect structures allow imaging of the time-dependent void evolution in inlaid copper interconnects. It is shown that void formation, growth and movement, and consequently degradation, depend on interface bonding and copper microstructure. Specific experiments were designed to study reliability-limiting degradation mechanisms in on-chip interconnects. In this paper, the challenges of copper microstructure monitoring and the study of degradation mechanisms, related to the reliability of the copper inlaid structures, are discussed. In particular, in-situ experiments to visualize mass transport and degradation in fully embedded copper via/line test structures are described. A model for void formation, growth and movement, and consequently interconnect degradation, is proposed. Electromigration lifetime can be drastically increased by changing or modifying the copper/capping layer interface.

Transmission electron microscopy (TEM) is increasingly used for characterizing structures that are shrunk continuously, especially microelectronic devices. Conventional focused ion beam technique (FIB technique) is used routinely in the semiconductor industry for time-efficient and reliable target preparation of TEM lamellas. The combination of FIB and lift-out technology using needle manipulators represents a new technical solution for sample preparation for 3-dimensional (3D-) TEM. The process steps for this are described in this article, requirements to optimal sample carriers are discussed and the suitability of the procedure is demonstrated by means of TEM images.

Defined mechanical and electrical properties can be achieved by alloying of aluminum and a subsequent thermo-mechanical treatment. The transmission electron microscopy is used for the characterization of the precipitations and dispersoides which determine these properties. Selected materials regions require special techniques for the preparation of samples. The TEM sample preparation of such regions using the focused ion beam-technique leads to excellent results in the TEM analysis. This will be illustrated through two examples.

Transmission electron microscopy (TEM) gains increasing importance in characterizing microelectronic components since the characteristic structures become smaller and smaller. Transmission electron microscopic investigations need specially prepared samples. The known conventional preparation techniques require a large amount of time. However, the Focused Ion Beam (FIB) method makes it possible to prepare samples for TEM within a short time and with a high success rate. In this paper, target preparation using the FIB method is described with reference to examples for VLSI components. Possible ways and limits of this preparation method are discussed subsequently.

Thin film and interface characterization are necessary in semiconductor industry to ensure high yields and the required reliability of the products. Particularly, the analysis of layer stacks is a challenging task. Transmission electron microscopy (TEM) essentially contributes to layer stack analysis in microelectronic products. Capabilities and limits of analytical TEM techniques as well as advanced TEM sample preparation techniques are discussed for front-end (MOS transistor) and back-end (interconnect) structures. Typical examples for advanced microprocessor devices are shown.

The atomic transport processes which could cause degradation mechanisms in Cu interconnects are described. The influence of interconnect line width, barrier type and anneal process on the microstructure and reliability of the inlaid Cu lines are discussed. Grain size and texture measurements have been performed at blanket films and at arrays of Cu lines using advanced analytical techniques. The median grain size decreases with decreasing line width, and it can be influenced by heat treatments. The crystallographic texture is predominantly {111} out-of-plane with sidewall-oriented grains in narrow Cu lines. The grains have an in-plane preferred orientation with the 〈110〉 direction parallel to the sidewall normal. The Cu texture is influenced by barrier structure and thickness.