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The ever increasing demand for wireless connectivity is leading to congested radio spectrum especially in the sub-6 GHz. This makes the interference problem a major challenge for wireless systems. This thesis targets hybrid analog digital beamforming receiver architectures to exploit the potential of spatial filtering for interference mitigation. We propose a new reconfigurable multi-beam architecture supporting both digital MIMO and analog spatial filtering. Spatial interference rejection is achieved using a set of flexible orthogonal beams with a programmable spatial-direction. RF/analog beamforming is realized by an improved constant-Gm vector modulator (VM). A 4-element 22-nm FD-SOI CMOS prototype MIMO Rx achieves widely tunable RF operating frequency range, covering much of the sub-6GHz bands (0.7-5.7 GHz). The Rx front-end also achieves a highly blocker tolerant performance with B1dB of -11.5 dBm, a high in-band linearity (in-notch IIP3 of +20 dBm), and a wide notch suppression bandwidth. A single-element noise figure of 5.5-7 dB is achieved on the vector modulator constellation corners. The chip of 0.52 mm2 active area consumes 77-139mW at an LO-frequency of 0.7-5.7 GHz from a 0.8V supply. We propose to characterize the interference robustness of MIMO receivers featuring hybrid analog-digital beamforming using EVM. This thesis also demonstrates the effectiveness of hybrid beamforming in interference mitigation utilizing adaptive Minimum Mean Square Error (MMSE) and Error Vector Magnitude (EVM) as an optimization criterion. Extensive EVM measurements carried out with a conductive set-up using a 4-element 22nm FD-SOI CMOS prototype MIMO receiver chip verify the performance of the adaptive MMSE algorithm. Over-the-Air (OTA) measurements with a linear 4-element dipole antenna array with half-wavelength spacing in the 2.4 GHz ISM-band quantify the improvement for real world scenarios, e.g., having a multipath propagation channel and mutual coupling between the antenna array elements. OTA results show that a rejection of 22.5 dB and 24.5 dB can be achieved on average in an in-door laboratory environment utilizing Vector Modulator (VM) constellations with 16 and 64 points, respectively.

The introduction of the internet of things (IoT) resulted in a significant increase in the demand for low-cost battery powered wireless transceivers. To decrease the cost of wireless transceivers, a full implementation on a single die or package, in a modern CMOS technology is preferred. However, with newer CMOS technologies both the maximum supply voltage and the breakdown voltage decrease, reducing the maximum achievable output power that the RF-PA can achieve from the nominal power-supply for a fixed load impedance. Switched mode class-E PAs are promising candidates for battery powered wireless devices, since they can ideally achieve 100% power efficiency and can be integrated in modern CMOS technologies. The performance and reliability of class-E PAs strongly depends on the load impedance, where load variations can reduce the performance and even permanently damage the RF-PA. To enable tuning and improving the performance and reliability of RF-PAs accurate information about its current operating conditions are required, which can be acquired from the internal nodes of the RF-PA. The focus of this work is on integrated measurement techniques, reliability improvements and linearisation for RF-PAs to enable efficient, robust and high-performance RF-PAs for use in modern wireless transceivers. A sampling technique to measure relevant internal RF-waveforms is presented. The acquired waveform information is later used to improve reliability and performance of a class-E PA. To improve the reliability of class-E PAs, a technique to self-protect the class-E PA by decreasing the PAs sensitivity to load variations is introduced. An on-chip switched-capacitor bank is used to tune the relative-resonance frequency of the switch-LC tank, minimizing the stress on the switch transistor over load variations, improving the reliability. A polar class-E PA with adaptive digital pre-distortion (ADPD) is presented, resulting in a reduction of the effect of load variations on the polar modulated class-E PA. The on-chip waveform characterizer is used to measure the internal drain voltage of the PA, after which the measured waveform is used to adaptively tune the DPD coefficients such that the RF-PA can maintain its performance over an VSWR up to 9:1.