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The article presents information related to computer programming language C. In the beginning, C was used much like Basic to solve simple computing problems for which there were no ready tools at hand, be they circuit-parameter calculations, algorithm simulations or shell scripts. A dialect of C can also be useful in modeling the movement of data through chips, as QLogic has found. C is so efficient at expressing the behavior of digital blocks, at least from a programmer's point of view, that it plays a key role in some verification flows even when it's not used at the architectural level. INSET: Coincidence, compromise and C.

The article reports that this week, on the Stanford University campus, a loosely knit organization of industry and university silicon gurus will conduct the 17th annual conference on the leading edge in performance silicon, aka Hot Chips. Over the years, Hot Chips has been a running index on the leading-edge ideas in the industry. Reduced instruction set computers first battled CISC here. Superscalar processors stepped into the glare at Hot Chips, as did the first powerful system-level ICs. Multithreading, multicore chips, and many ideas that never reached the big time all appeared, in their turns, at Hot Chips.

The article discusses about electronic paper. The story of electronic paper (e-paper), so far, has proved to be what could be termed techno-hyperenthusiasm. Electronically rewritable paper requires two basic components. A substrate and something electrically controllable that can serve as the ink. If the epaper material has good enough image retention, it can be written by a device analogous to a printer, and then taken out and used just like a normal sheet of paper.

Focuses on the impact of configurable computer systems on the changing flow of data or algorithms. Definition of configurability; Distinct category of reconfigurable systems; Operation of the system at installation.

Focuses on the debate over embedded dynamic random access memory (DRAM). Portfolio of strengths; Speed improvement from embedding the DRAM array; Output complications. INSET: ASIC vendors explore alternatives..

Focuses on the convergence of dynamic random access memory (DRAM) variants in the graphics frame buffer of personal computers. Extended-data-out DRAM; Synchronous DRAM; RAmbus DRAM; Choice of frame buffer memory; Limitation in alternatives; Controller chip.

Reports on researchers' entry into the 0.9-V realm of electric batteries. Applications; Comparison with 3.3 V; Economic of customer demand; Technological challenges; Standardization issues; Timing difficulties; Projections on vendors making 0.9-V parts in 1996.

Discusses the design choices and challenges offered to personal computer vendors by Intel Corp.'s family of Pentium microprocessors. Internal speed realization; Thermal management; Cache design differences with the 486 processor; Zero-wait-state timing; Tagging of the random access memory (RAM); Review of the input/output (I/O) subsystem.

Discusses the personal computer industry's search for bandwidth as discussed in the second annual Silicon Valley PC Design Conference, 1993. Equality among designers in concerns and level of sophistication; Shift to notebook and palmtop design; Achievement of the latest microprocessor's full performance potential; Limited affordability of CPU designer in terms increases in L1 cache size; i486 and Pentium; More.

Discusses the importance of reusable intellectual property (IP) for the computer industry of the United States. Estimated growth of commercial IP from 1998 to 2001; Benefits of reusable IP to application specific integrated circuits (ASIC) business; Licensing strategy developed by Motorola Corp. for its IP.

Focuses on the development of single electronic chip systems through the use of core technology. Definition of core; Benefits; Applications; Commonly used cores; Comment by Ranier Fehr, consultant at Ascom Technology; Core development projects by different companies; Issues facing the development of core-based application specific integrated circuits.

Reports that memory demands of multimedia systems have frame-buffer designers beating the bushes for faster varieties of DRAMs. Designers seeking synchronous DRAM (SDRAM) or Rambus DRAM; Information on row-access and column address.

The article focuses on the problems of benchmarking embedded systems. Benchmarking embedded systems has always been difficult. As those simple MPUs of yore have evolved into complex, multitasking systems-on-chip (SoC), often with hardware accelerators, shared on-chip memory structures and buses, and intelligent peripherals, the simple question of whether a given chip can do the job has become a huge issue. The Embedded Microprocessor Benchmark Consortium is taking on these challenges. With three major initiatives, the group hopes to create new, open and licensable benchmarks that will be predictive for the multicore SoCs and sophisticated applications that characterize the current market. The three primary areas for benchmarking, namely, automotive control, multicore SoCs and storage controllers.

The article presents information related to various new venture capital firms. Kleiner Perkins Caufield and Byers has become the benchmark people use to rate everyone else. In part it's a matter of longevity and reputation, especially the near-legendary reputation of partner Vinod Khosla. US Venture Partners was hailed for its general partners' strong domain expertise. Broad-ranging Foundation Capital claims all of its principals have been operating executives at one time or another.

This article reports that private equity's rising profile in technology investments became palpable this summer, as Agilent Technologies Inc. sold its semiconductor group to two buyout firms and as former U.S. Federal Communications Commission chairman Michael Powell joined Providence Equity Partners Inc., with $9 billion in telecom and media holdings. Equity firms' role in technology investment once was limited to the occasional buyout of a semiconductor company by such leading lights as Texas Pacific Group Inc. In the deal-laden 1990s, a company that had been through two or three rounds of venture financing usually could depend on an initial public offering in a roaring Nasdaq market or on acquisition by a larger company.

Presents an interview with Scott Adams, associated with the engineers' comic strip "Dilbert." Professional background of Adams; Views of Adams that the strip is very sympathetic to the lives of its engineers; Plans of Adams to use those situations in the comic strip that would have broad applicability to people in the office environment.

This article reports that Paolo Gargini, the Intel Corp. manager chairs the effort to define the book "International Technology Roadmap for Semiconductors" (ITRS). If the road map committee has its way, individual chip-manufacturing process nodes will soon be relegated to the industry's scrap heap, alongside megahertz ratings for microprocessors and other outmoded metrics. At a meeting here last week to consider a draft 2005 edition of the ITRS, which serves as the semiconductor industry's technology development bible, the committee instead outlined "cycles" for DRAM, flash and logic chips. Intel's Gargini said that from the early 1970s to the mid-1990s, the industry would shrink the linear dimensions of the half-pitch by 30 percent every three years.

The article analyzes different reasons why people in the U.S. are taking to learning the Mandarin language. Chris Chene, senior director of marketing at Sharp Microelectronics decided to learn Mandarin because he believes that there is design as well as production going on in China today. Other Westerners who have taken on Mandarin agree that the first contact can be daunting. Mark LaPedus, editor of Silicon Strategies, had personal reasons for sticking with it. LaPedus took a route not readily available in the States: Mandarin immersion classes, which are offered in Taiwan to foreigners who want to learn the language and can work intensively on it.

The article focuses on semiconductor Internet Protocol (IP). Simple arithmetic can show the necessity for intellectual-property reuse in system-level chip design. Unless substantial portions of the chip are reused from previous designs or licensed from third parties, either the design team will grow to the Intelesque scale or the schedule will span a geological time frame. But arithmetic doesn't capture the enormity of finding, qualifying and reusing IP. Colin Harris, vice president of worldwide operations at PMC-Sierra Inc., said his organization has made a policy of acquiring IP for supposedly stable blocks, such as standard interfaces, where PMC's engineers could add little customer-visible value and where one would think IP quality should be reasonable. One of the most formidable undertakings for any SoC design team today is the identification, evaluation and selection of IP. The process in dealing with this risk often involves market searches, checklists, interviews and internal evaluations. One help in this area are IP exchanges, such as www.us.design-reuse.com, partially owned by CMP Media LLC.

The article presents information on system-on-chip (SoC) platforms. End markets are presenting a serious problem to traditional ASIC design. One strategy suggested for beating this problem is to embed a portion of configurable logic and memory into an SoC. In this way a single, platform SoC can be designed that spans a wide range of markets. The configurable portion of the chip can then be used to fit the platform ASIC to a particular market. An eASIC fabric has been designed into a ISO-nanometer, six- metal platform SoC along with an ARM 946 CPU, an Amba bus architecture and some general-purpose peripherals. An important part of the effort was to define macros at the physical interface between the platform logic and the eASIC fabric that permitted the two to be analyzed separately for signal integrity.

The article focuses on the intellectual-property (IP) law or the patent process. Protecting one's own or an employer's IP is crucial in today's global marketplace, IP and patent experts say, and engineers would do well to consider the possibility sooner rather than later. In the U.S., unlike in many other countries, precedence is decided by the date of invention, not by the filing date to the patent office. If an application covers pioneering work, it makes sense for the claims to be broad. But the broader the claims, the longer it will take the patent office to evaluate them and the more likely it is they will conflict with a previously granted patent or some prior art. INSET: History lives at the PTO.

Interviews Steve Furber, professor of computer engineering at the University of Manchester. Origin of his interest in computer architecture; Link between asynchronous central processing units and systems of neurons; Efforts at exploring asynchronous design at the University of Manchester.

Reports that computer system designers are lobbying for a move from rule-based inspection of completed design files to design-for-yield, which are anchored in process models throughout the flow. Absence of enabling tools which threatened to stall widespread adoption of the 90-nanometer node; Number of rules for IBM Corp.'s 90-nanometer process for the Metal-2 layer; Transfer patterns for lithography.

Focuses on the Bush administration's establishment of a commission to supervise human expedition to Mars in 2020. Emphasis on robotic orbital and lunar flights; Importance of electronics in the renewed manned-space-flight program; Transmission for electromagnetic communications; U.S. National Aeronautics and Space Administration's application of incremental strategy to test manned vehicles for Mars.

Presents a debate regarding system-in-package (SIP) versus system-on-chip (SOC), involving Philips executive Pieter Hooijmans and Texas Instruments Inc. executive Bill Krenik. Best strategy for constrained mobile wireless devices; Transition from 90 nm to 65 nm; Ability to choose the optimum process per function; Digital circuitry to assist radio frequency.

Interviews eSilicon Corp.'s chairman, president and chief executive officer Jack Harding. Performance of the company as a general contractor for chip companies in the United States. Views on the case of public policy on education; Ideas on improving the expected value of an investment portfolio for a venture investor; Future business plans.

Reports the announcement of Intel Corp. to shift in emphasis from ever-increasing single-processor performance to on-chip multiprocessing in the U.S. Differences in the scale of personal computer from a single CPU on a die to multi-CPU for high performance computing; Contention of IBM Corp. chief technologist that the CPU speed and performance is dependent on the application; Details of the computer architecture of the Power5.

Provides information about the list of the most notable startups in the electronic industry in the U.S. for year 2005 compiled by "EETimes." Creation of a network-on-a-chip interconnect design; Technological advancements for electronic dispersion compensation; Development plans on well-backed startups targeting semiconductor memory.

This article focuses on the issue of intellectual property rights as faced by International Business Machines Corp. (IBM). A move by IBM Corp. last week toward a "patent commons" for software has rekindled a long-simmering debate about how best to manage intellectual property within the electronics industry. While IBM has come down on the side of patent pools, others think indemnification plans, prior-art repositories or even legislation are a better bet. So far, no route cleanly does it all. The news sparked hopes among some industry watchers that companies could collectively find a saner way of handling IP rights.

Focuses on the controversy behind the decision of Intel Corp. to take the hydra-headed designs known as multicore processors into the volume realm. Declaration of Paul Otellini, Intel president, on the microprocessors; Software cost; New features.

Reports on the revival of third-party logic-cell libraries and memory intellectual property in the United States. Announcements made by Prolific Inc. and Artisan Components Inc.

Describes future systems-on-chip (SoC) technology. Advanced SoC functionality; Overview of the SoC concept; SoC Alternatives; SoC applications.

Cites the unveiling of Sonic Inc.'s third generation Silicon Back-plane interblock communications architecture. Design of the computer interface to address the flow of data between functional blocks on a system chip design; Advantage of the interface in owning a collection of physical interconnect traffic-shaping agents; Offer to designers a choice of bond to tie together cores and intellectual property blocks.

Reports that a patent granted to PalmChip Corp. covers the techniques used to implement on-chip computer processing unit (CPU) bus structures in nearly all modern system-on-chip designs in the U.S. On-chip interconnect structure for linking CPUs, memories and peripheral devices; Use of unidirectional buses with centralized memory controllers; Implications of the patent.

Focuses on developments in system-on-chip interfaces. Three main branches of the software-defined input/output family; Critical factor in implementing the interface; Emergence of microcontrollers equipped with integrated programmable-logic fabrics.

Reports that six chip vendors have started offering structured application specific integrated circuits (ASIC) that have the density, performance and power efficiency of cell-based ASIC but with shorter turnaround time and lower nonrecurring expense. Description of structured ASIC; Features and capabilities of ASIC products from AMI Semiconductor, Chip Express, Lightspeed Semiconductor and NEC Electronics, Altera Corp. and LSI Logic Corp.

Reports on the rivalry between Intel Corp. and IBM Corp. in developing 90-nanometer Complementary metal oxide semiconductors. IBM's silicon-on-insulator approach; Details on Intel's strained silicon technology.

Reports on Chip Designs Ltd.'s launch of a massively parallel array of heterogeneous processors that it believes will jettison digital signal processing, field programmable gate arrays and application-specific integrated circuit incumbents from the third-generation basestation designs. Processing capabilities; Tools and development environment; Potential applications.

Discusses the evolution of system-on-chip designs in the field of electronic engineering. Background on component-based design; Arrival of the microprocessor; Overview of the register-transfer level approach to implementing design requirements.

Reports on the proliferation of failure modes being observed in very deep-submicron processes on system-on-Chip (SoC) testing. Problems created by the growing attempts to reuse Internet Protocol; Manifestations of problems with subwavelength lithography and aggressive geometries; Example of SoC testing problems experienced by automobile manufacturers.

Highlights the 2002 International Solid-State Circuits Conference (ISSCC). Papers released by Sun Microsystems Inc. and Fujitsu Ltd.; Semiconductor manufacturing process developed by Intel Corp.; Demonstration on complementary oxide semiconductor technology.

Focuses on the effects of business cycle and business models on semiconductor intellectual-property (IP) vendors. IP business model of ARM Ltd.; Factors that influence the profitability of vendors; Failures in the business models of IP vendors.

Focuses on the 11th Institute of Electrical and Electronics Engineers (IEEE) applications specific integrated circuit (ASIC) Conference in Rochester, New York. Discussion on fundamental problems inherent in the coming age of integration levels; Presentation made by David England of Intel Corp.; Focus on power consumption.

Comments on the demise of the standalone microprocessor after 20 years of unchallenged dominance. The vestiges that remain; The role of traditional, monolithic X86 CPUs; The shift toward the CPU as a core embedded in ASIC; Selecting a microprocessor; Hyundai's decision to use a 32-bit RISC core in its monolithic MPEG-2 decoder; More.

Reports on the efforts of University of California's Kodak Berkeley Research to improve the Reed-Solomon approach to error correction. Views from researchers; Domain of forward error correction; Systems approach. INSET: Reed-Solomon..

Reports on Apple Computers' rollout of its PowerMac Systems, a blueprint for using software emulation to ease aa new processor into an existing software base. PowerPC clock required by an emulator to execute a 68k instruction; Cache tracking problems; Emulation platform supported by RISC purists.

Focuses on design choices to be considered on the use of computer memory alternatives. Controller design; Row access; Board layout; Sub-system partitioning; Pixel depth.

Reports on the application of flash-memory technology to other chips. Disagreements among vendors with different flash architectures; Unique features; Density comparison; Problems; Challenge in combining the processes; Flash as an alternative for microcontrollers; Migration into the analog world. INSET: How flash evolved from the world of EPROM..

Focuses on processor designers' increase of the number of instructions per cycle of microprocessors to enhance performance. Design and renaming issues; Technical challenges; Success factors; Benefits and applications.

Reports on LSI Logic Corp.'s development deal with Synopsis Incorporated. Development of a design capability that breaks some key timing and layout barriers at the submicron level; Synopsis Inc.'s deals with other companies; Development of new synthesis libraries.