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Silicon wafers are a key component in integrated circuits which comprised of various electronic components that are arranged to perform a specific function. Wafer dicing is a mechanical process of removing material from a wafer by synthetic diamonds as abrasive particles. Chipping along the cut line crucial to the wafer dicing operation has been identified by semiconductor manufacturers as a relevant area for improvement. The purposed of this study is to characterize the effect of dicing operation on the optical silicon wafer coating material. The effect of the blade wear and silicon wafer kerf width will be analyzed in this work

With the gaining demand for SiC semiconductor devices it is more and more challenging to meet the requirements for SiC volume production with the state of the art wafer dicing technology. In order to overcome this challenge the laser based dicing technology Thermal Laser Separation (TLS-DicingTM) was assessed for SiC volume production within the European project SEA4KET. This paper presents the key results of this project. It could be demonstrated that the demand of SiC volume production regarding throughput and cost as well as edge quality and electrical performance of diced chips can be met with TLS-DicingTM.

The grinding of riblets with multiple profiled grinding wheels is an efficient method to minimize the fluid friction on surfaces. In turbo machinery components, like pump impellers or compressor blades, the riblets must be ground with a curved tool path since the flow is rarely linear on such surfaces. This leads to angular errors in the generated riblet profiles and therefore requires the use of grinding wheels with smaller diameters. The tool wear increases due to lateral strain on the peaks of the grinding wheel. Consequently, the increased wear and the need of smaller tool diameters decrease the efficiency of the process. In this paper a structuring process with dicing blades was investigated in order to increase the economic viability of this process. A dressing operation for such tools is not necessary and thus reduces the non-productive time of the manufacturing process. Furthermore, profile tip wear has no negative effects on the aspect ratio of the generated riblets since the riblet geometry is determined by the thickness of the dicing blades.

Hydride Vapor Phase Epitaxy (HVPE) was used to grow 1-4 μm thick undoped GaN layers on 4H-SiC and sapphire substrates. To adjust mechanical strain and crack formation in the GaN/SiC samples, the AlGaN-based buffer layer was grown at low temperature (920-980°C) and the GaN layer was grown at a higher temperature (1000-1040°C). Laser scribing through the GaN layer or the SiC substrate was applied to fabricate dies from the GaN/SiC and GaN/sapphire samples. The laser irradiation passing through the GaN layer to the sapphire substrate or through the SiC substrate to the GaN layer, along two orthogonal directions created a net of micro-cavities in sapphire and melted grooves in SiC that promote easy breakage of the sample into rectangular dies.

A novel dicing technology that utilizes femtosecond pulsed lasers (FSPLs) are demonstrated as a high-speed and cost-effective dicing process for SiC wafers. The developed dicing process consists of cleavage groove formation on a SiC wafer surface by the FSPL, followed by chip separation by pressing a cleavage blade. The effective FSPL scan speed on the SiC surfaces was 33 mm/s. Kerf loss can be negligible in the developed FSPL dicing process. In addition, the residual lattice strain in the FSPL-diced SiC chips was comparably small to that of the conventional mechanical process using diamond saws, due to the absence of the lattice heating effect in femtosecond-laser processes.

One challenge for volume manufacturing of 4H-SiC devices is the state-of-the-art wafer dicing technology – the mechanical blade dicing which suffers from high tool wear and low feed rates. In this paper we discuss Thermal Laser Separation (TLS) as a novel dicing technology for large scale production of SiC devices. We compare the latest TLS experimental data resulting from fully processed 4H-SiC wafers with results obtained by mechanical dicing technology. Especially typical product relevant features like process control monitoring (PCM) structures and backside metallization, quality of diced SiC-devices as well as productivity are considered. It could be shown that with feed rates up to two orders of magnitude higher than state-of-the-art, no tool wear and high quality of diced chips, TLS has a very promising potential to fulfill the demands of volume manufacturing of 4H-SiC devices.

GaN High Electron Mobility Transistors (HEMTs) on SiC have gained remarkable attention as these devices are revolutionizing the power and radio frequency (RF) electronics markets. Although significant advances have been made in transistor technology innovations, innovations pertaining to the backside process technology have been noticeably few. This paper will address and focus on innovations in the backside processing of GaN on SiC devices. A series of innovations in backside processing enable through SiC and GaN via etch rates to exceed 1.5 micron/minute. Wafer dicing process innovations afforded a >4x improvement in sawing throughput and a >6x improvement in blade lifetime through the novel addition of ultrasonic power to a conventional sawing tool.

Mechanical blade dicing is a state-of-the-art technique for the chip separation of SiC devices. Due to the hardness of SiC this technique suffers from low feed rate and high wear of the diamond coated dicing blade, resulting in the risk of uncontrolled tool breakage during the dicing process. With the upcoming transition to 150 mm diameter of SiC wafers this technique will most probably reach its limit. For dicing SiC wafers of those diameters on a productive scale three alternative dicing technologies are considered in this paper: ablation laser dicing, Stealth Dicing and Thermal Laser Separation. All these methods are based on laser processing. The benefits of these technologies are discussed in detail and compared to the classical mechanical diamond blade dicing, including a brief summary of first experimental results on each of the three laser dicing technologies.

The precision dicing machine is adopted as the research object in the paper, the technology of grating sensor is selected to overcome the shortcoming of traditional compensation methods for inaccurate return compensate. The measurement is done through the grating sensor, with the aid of neural network feedback method, the fitting and compensation of the data measured by the grating sensor is completed, the deviation caused by vibration during the spindle run-time is eliminated. And the purpose of improving the precision of spindle is realized.

The neural probe array is an important tool for getting the neural signals. Giving consideration to the biological compatibility and the demand of integrating in circuit, new fabrication process of a silicon-based three-dimension neural probe array was reported. The idea about milling in mechanical process and the method of structure for transfer were introduced in the fabrication. The 10*10 scale silicon-based three-dimension probe arrays integrated in the readout circuit directly were fabricated by means of flip chip and multi-blade mixing dicing techniques. In the entire fabrication process, no any high-temperature process and silicon wet etching process, which would damage the circuit, were included. Using the fabrication process above, the 10*10 scale silicon-based probe arrays with centre-to-centre separation of 400 μm were achieved. In the probe arrays, whose good rate was more than 95%, the width of a single probe was 100 μm, the tip angle was 25o, and the height was more than 1.4 mm. Through the fabrication process, it was not only reducing the pin count greatly, but also simplifying the interface effectively. By the in vivo experiment of the Sprague Dawley rat, the corresponding nerve signal was obtained.

UV laser dicing has many advantages such as mechanical stress-free and dicing shape-free, but it is seldom used to dice multi-layer MEMS wafers because of the deposition of a lot of debris and heat affected zones around the dicing lines. In this paper, a novel UV laser dicing method for anodically bonded wafers is presented. The heat caused split of the bonded silicon and glass around the dicing line is prevented by fabricating recesses on either the glass wafer or the silicon wafer. The Finite Element Method (FEM) in the ANSYSTM software was utilized to analyze the temperature and thermal stress distributions during the dicing process. The thermal stress is minimized sharply due to the fabrication of the recesses beneath the dicing line. The thicknesses of the glass and silicon wafers are 500μm and 250μm, respectively. The anodically bonding temperature is 360oC, and the bonding voltage is 400V. Dicing experiments show that the huge thermal stress caused by the laser can split the originally bonded silicon from glass around the dicing line. After recesses are fabricated along the dicing line, no heat caused split happens. The experiment results are in a good agreement with the FEM simulation. Compared with other methods, this research can provide a more reliable, flexible and cheaper laser dicing process for thick anodically bonded silicon/glass MEMS wafers, especially for multi-layer wafers with free shape.

wafer processing is one process of the IC industry which is a booming area nowadays, the quality of the production of this course depends on the performance of the film which is formed by deposition. And one of the most important factors influencing the performance is working pressure. Variable structure chamber for flowing experiment and testing which is a multifunction testing platform with changeable structure and sufficient measurement points all-covered the chamber, a device has been designed and manufactured to measure and research vacuum flow filed. By using this equipment, the pressure in vacuum chamber could be measured precisely and promptly, thus relationships among the size and shape of the chamber, the pressure, and the gauges would be clear, there would be helpful for vacuum measurement. Background The course of manufacturing a chip of IC production including 400~500 processes which could be divide into two categories: wafer processing which is FEOL (front-end-of-line) and chip packaging which is BEOL (back end of line), as it illustrated in Fig. 1. Wafer manufacturing is a process of exacting and refining high purity silicon (usually 99.999%) from silica; Wafer processing is depositing a thin film (among 100umto 22nm, according to the requirement and depending on technology) which contains required elements on the face of the original wafer; Dicing is chipping out wafer into little blockages to face different requirement; Assemble and packaging is fabricating chip into IC component. During the course of Wafer processing, the working condition is usually under low velocity, high vacuum and high temperature condition (depends on the characteristics of sediment), take the projectDeposition of Hydrogenated Amorphous Siliconas an example---- 5.0sccm, 11.0~16.0mtor, and 250°C[1]. The performance of wafer is decided by the nature of reactors and the processing condition of which a little change would lead a different property of the production. Thus it is necessary and imperative to figure out the relationship among the factors influencing depositing process. And the most important among these factors are pressure, velocity, and temperature. In this paper, a method of pressure measurement based on a device of variable structure chamber for flowing experiment and testing will be introduced. Fig. 1, Semiconductor manufacturing process

In the silicon wafer polishing process, the mounting of wafer on the polishing head could be greatly influential in final quality of finished wafers. This paper focuses on the waxless wafer mounting technique which could replace the traditional wax wafer mounting. Mounting of wafers on the carrier block using a wetted porous template provides a simple way of securing wafer on polishing head for precision wafer polishing. Demounting of wafers from the porous pad is carried out by using the water jet impingement which takes only a couple of seconds for wafer demounting. A series of wafer polishing tests of 8 inch silicon wafers using the present wafer mounting system found that the developed waxless wafer mounting could be quite suitable for producing the wafers of the excellent surface qualities by meeting industry standard such as SBIR, LLS, and production yield.

We present a single mask selective release process for complex SOI MEMS device. Comparing to the one-step dry release process, there are two improvements, the first one is to ensure that the bottom of the suspension beams will not be notching, and have sufficient strength and rigidity, the second one is to ensure that the released structures will not be damaged during wafer dicing. According to the proposed design rules, in the dry release step, most of the device area is released, except the boundaries of the proof mass and the suspension beams. Then, in the wet release step, all the structures will be released, and also increased the gap below the structure. So the suspension beams is protect enabled that the device has sufficient rigidity and not easy to break. To verify this method, a micromachined gyroscope is fabricated and test.

Complex woodworking curve saw plays an important role in wood processing. In order to provide a preliminary test and verification tools for curve saw processing technology, a research on complicated curve saw movement and cutting simulation based on virtual environment was conducted. Firstly, constructed the mathematical model of all movement axis, solved the motion law of between dicing saw and work piece by matrix arithmetic. To obtain a better graphics effect in cutting process, a dynamic mesh model based on self adaptive quad-tree was put forward. Finally the simulation system was achieved in the platform Microsoft Visual Studio 2010 and OpenGL which has a good effect and can meet the validation requirements of curve saw.

Moore’s law by scaling conventional CMOS involves huge lots of technology evolution in both aspects of electronics material and micromachining. One of the most promising modern innovations is the 3D IC and the key material to the 3D IC is the low-K (dielectric) materials. Since the new generation low-K material is rather porous and fragile in structure strength, conventional singulation methods including the dicing saw and nano-second laser can not be applied. New machine modality has to be used to avoid the cracking and excessive debris contamination. In this paper we demonstrate the application of pico-second laser on the grooving machining of low-K wafer. The results show that the removal of low-K material is up to the production standard: smooth groove bottom with minimal debris. However, as the groove line involves metal pads the laser power is partially consumed by the ablation of the metallic material the depth is not controlled ideally. With proper adjustment of the machine parameter such as laser power, focal depth and pulse energy the problem can be resolved.

Mainly introduce the work principle of Dicing Saw and the different kinds of errors in assembly ,analyze all errors which influence LCD glass ; draw the picture according to the measuring data ,from the picture estimate the errors how to come from and prove that the judgments is true through calculating the rigidity of liner bearing ;find the source of the main error ,appoint out how to take measures for the errors and what is the key point in the assemble. This errors analysis method of the applied mechanics play an important role in other Dicing Saw assemble and test .

Silicon carbide (SiC) is a promising semiconductor material for high-temperature, high-frequency, high-power, and energy-saving applications. However, because the hardness and chemical stability of SiC are high, few conventional machining methods can handle this material efficiently. We previously developed a plasma chemical vaporization machining (PCVM) technique, which is an atmospheric-pressure plasma etching process, and investigated its application to the processing of SiC substrates. In this paper, we propose a novel style of PCVM technique for dicing, using slit apertures to confine the plasma. From experiments by means of an apparatus with a one-slit aperture formed by two masks, it was found that the kerf loss was almost proportional to the slit width, and that the etching depth increased with RF power. Furthermore, from experiments on a SiC wafer, we obtained a 130-μm etching depth and 300-μm kerf loss for an 11-min processing time and 200-μm slit width.

Dicing blades are widely used for cutting brittle materials, such as silicon, ceramics, sapphire and optical glass. In order to reduce the production cost in semi-conductor processing, the substrate of semi-conductor was changed to large diameter. High cutting speed and small loss of material are desired for the dicing processing. To achieve a large safety margin and increase the rate of material utilization, thin dicing blades with fine abrasives are commonly used. The thin dicing blades, however, break down very easily. Thus, it has to be handled with care. In this study, a series of reinforced thin dicing blades with various films were proposed for improving the handling ability and grooving performance. The vibration properties of blades were investigated, too. According to the results, cutting loss and chipping size were reduced by reinforced blades and the higher the damping ratio, the smaller the chipping size.

To meet the large current handling requirements of modern power conditioning systems, paralleling of a large number of devices is required. This increases cost and complexity through dicing, soldering, and forming multiple wire bonds. Furthermore, paralleling discrete devices increases package volume/weight and reduces power density. To overcome these complexities, PiN diodes were designed, fabricated at high yields, tested, and interconnected on a three-inch 4H-SiC wafer to form an 11.72 cm2 wafer-scale diode. The wafer-scale diode exhibited a breakdown voltage of 1790 V at an extremely low leakage current density of less than 0.002 mA/cm2. Under pulsed conditions, the peak current through the wafer-scale diode is 64.3 kA with a forward voltage drop of 10.3 V. The dissipated energy was 382 J and the action exceeded 1.7 MA2-sec.

Modern power conditioning systems require large active area devices which can support high currents. Though the breakdown and thermal properties of SiC make it an excellent choice for power switching applications, active area size is currently limited due to material and processing defects. One alternative is to parallel discrete diced die to achieve large active areas. However, this increases cost and complexity through dicing, soldering, and forming multiple wire bonds. Furthermore, paralleling discrete devices increases package volume/weight and reduces power density. To overcome these issues and achieve devices of high current switching capabilities, thyristors were designed and fabricated for the purpose of wafer-scale interconnection - which avoids the need of dicing and bonding and can achieve significant current density improvement over the paralleled diced device approach. Discrete thyristors fabricated for interconnection exhibited excellent yields and good uniformity of both blocking and on-state characteristics, showing great promise for large-scale interconnection.

Silicon carbide (SiC) is a promising semiconductor material for high-temperature, high-frequency, high-power, and energy-saving applications. However, it is so hard and chemically stable that there are few efficient conventional machining methods for it. We have developed plasma chemical vaporization machining (PCVM), an atmospheric-pressure plasma etching process, and investigated its application to the processing of SiC substrates. In this paper, the cutting characteristics of a SiC substrate by PCVM with a wire electrode are described. We found that increasing the rf power and reactive gas concentration increases the etch rate and that the etch width can be reduces by increasing the SF6 concentration. The maximum etch rate was 2.1 μm/min and the minimum etch width was 220 μm. It was also demonstrated that a SiC wafer prethinned to 100 μm can be successfully cut without breaking or cracking.

In this article, a new technique for controlling crack position and its propagation direction in solder-bonding using Al/Ni exothermic reaction is described. Sputtered Al/Ni multilayer film is able to produce heat instantly by its self-propagating exothermic reaction, and the reactive film can be used as heat source for solder-bonding. During the reaction, however, volume reduction by approximately 12% occurs due to crystal structural change from fcc to bcc and lattice-spacing reduction. Consequently, cracks are produced in the reacted NiAl structure. The cracks negatively affect the strength of the bonded system. We have found a new technique for controlling crack position and its propagation direction. Multiple ignitions for reaction demonstrated that cracks in reacted NiAl film can be controlled. When applying the flash heating technique to wafer-level bonding, cracks are probably produced. If cracks can be fabricated on dicing cut lines by using the simultaneous multiple reactions technique, crack-less solder-bonded Si hermetic packages would be realized.

Wafer pre-aligner plays an important role in wafer manufacture. Wafer pre-aligner positions wafers accurately before they are transferred onto exposure platform, and the positioning accuracy greatly affects the exposure accuracy of wafer and the work efficiency of the whole manufacture system. The paper makes an overview on wafer pre-aligner from the following aspects: working principle, mechanical structure, machine vision and the algorithm on the detection of wafer edge.

In the manufacturing of slider, the final step is a dicing process of the rowbars into individual slider. However, in all slider separation processes seem to affect the curvature of the slider air bearing surface (ABS). As a result, the change in ABS crown and camber which can significantly affect the fly height of the slider. This paper investigates the influence of three types of dicing process, with the same feed rate and cutting speed, on the ABS curvature.

The experiments on dicing monocrystalline silicon wafer using micro abrasive water jet turning were performed. A specifically designed water jet machine tool with four axes was developed and a specially designed cutting head has developed, in which the inside diameter of orifice and focusing tube is f125 mm and f500 mm respectively, while the silicon carbide solid abrasives with average diameter of 25-100 mm was used. In order to control the flow rate of micro abrasives precisely, an abrasive feed system with auger mechanism driven by DC motor reducer was used. The diameters of monocrystalline silicon bars are around 50 mm. Two basic turning methods, i.e. turning with stationary jet and turning with moving jet were applied. The preliminary experimental results such as kerf width, wafer thickness, surface quality etc. were analyzed. It was found that micro abrasive water jet can be used to precisely turn brittle materials like monocrystalline silicon. The turned wafer with thickness of 1 mm above could be achieved. A thinner wafer less than 1 mm is difficult to obtain during experiments because of cracking or chipping. Experiments demonstrate that the wafer surface has macro stripping characteristics similar to linear cutting. It was observed that there is less waviness and smooth surface on the turned wafer when with moving jet. And it depends greatly on the water jet pressure, feed rate of the jet, rotation speed of silicon bar, abrasive particle size as well as flow rate of abrasive. The detailed analysis indicates that the surface roughness of turned wafer with moving jet is around Ra 1.5-5.6 μm, while that of turned wafer with stationary jet is around Ra6.3 μm, when other conditions are same. The results show that surface quality turning with moving jet is obviously better than that of stationary jet. Smaller surface roughness of turned wafer could be obtained when finer abrasive is used. The experiment shows also that the wafer is typically tapered with either the stationary jet or moving jet. There is a concave on the turned surface when feed rate of the jet is too low or dwell time is too long. This is attributed to the jet rebound from one face to the other. Therefore there is an optimizing rotational speed during turning. This study indicates that dicing mono crystalline silicon wafer using micro abrasive water jet turning has potential application in semiconductor industry.

Biopotential signals in shin tissue reflect the body’s healthy conditions. So the measurement of these signals can diagnose whether the body has diseases or not. Traditional technology used to measure these signals results in pain, bleeding, infection, etc. Recently, the microneedle electrodes are used to measure these signals owing to their advantages, such as painless, low cost, easily made, etc. This paper presents a new method to fabricate the silicon-based microneedle array electrodes intended for measuring biopotential signals in the skin tissue. The arrays consist of a 5 mm x 5 mm silicon base with gold film, and 49 silicon needle-type electrodes with gold film in a 7x 7 array on the silicon base. Each needle is approximately 700 μm long, 70μm in diameter at the base. The 1mm-thick silicon wafer is cut to form 300x 300 x700 μm rectangular micro-column by dicing saw. Then the 5x5 mm silicon base with these columns is cut off to form the whole substrate. The rectangular micro-columns are etched in the mixture acid solution (HNO3 and HF) until getting sharp microneedles. Then the surface of the microneedles is sputtered the gold film, the microneedle electrodes are formed. One array of these electrodes exhibits low impedance for measuringbiopotential signals.

Piezoelectric sensor can produce voltage when deflected (function as an energy harvester) while piezoelectric actuator can deflect when a voltage is applied. Different device applications have different requirements on the thickness and in-plane geometry of the Lead Zirconate Titanate(PZT) piezoelectric layers and thus have their own processing difficulties. In this paper, PZT-Au-Si cantilever is fabricated by eutectic bonding and dicing process.The properties of lapped PZT ceramics and silicon cantilever is also evaluated. The PZT-Au-Si cantilever applications for both piezoelectric actuators and energy harvesters have been confirmed.

This research investigates machining schemes for dicing soda lime glass in order to reduce the damage in the processes. Ductile machining and brittle machining of glass are first analyzed based on fracture mechanics and then verified by experiments. Experiments with various machining schemes including scribing-then-breaking, direct-dicing and dicing-then-breaking processes for soda lime glass are then conducted. Experimental observations showed the following results. (i) The critical depth of cut (CDOC) for soda lime glass is between 0.4μm and 0.8μm that matches theoretical prediction, 0.78μm, based on fracture analysis. (ii) The scribing-then-breaking machining scheme results in less damage than the regular slicing process. The DOC of scribing, however, must be in the ductile-brittle region to achieve this result. (iii) Defect due to dicing on the back surface is higher than that on the front surface in one-step dicing through process. Dicing defects can be effectively reduced by decreasing the feed rate or increasing the dicing speed.

This paper describes evaluation of the strength in Ag-Sn-jointed Si specimens heated by Al/Ni film’s exothermic reaction. The reaction generates heat enough to melt Ag-Sn film for soldering. To measure the strength, four-point micro-bending test technique has been developed. The rectangular-solid Si specimens having a Ag-Sn/AlNi/Ag-Sn section were prepared by dicing the bonded Si-wafer under various pressure loads. A higher pressure yielded a better contact condition between Al/Ni and Ag-Sn so that heat-conduction improved; consequently Ag-Sn was melted sufficiently. Al/Ni reactive film has a potential as a micro-heater in soldering for MEMS.

Laser micromachining has been widely used for micro-component fabrication of various materials, such as silicon substrates where silicon wafer is ablated accurately and precisely through marking, scribing, drilling or dicing. Thermal damages can occur on the substrates when improper process parameters and methods are used. This paper presents a review on the micromachining of silicon substrates using conventional and novel lasers as well as water-assisted laser micromachining technologies. The basic concepts and approaches of the technologies are discussed along with the challenges to damage-free laser micromachining at commercially acceptable cutting rates.

In this paper, the comparative experimental research on DPSS UV laser (wavelength is 355nm) and high-pressure water-assisted YAG laser dicing SiC wafer was done. The results show that is strict with the performance of laser source and the dicing technique parameters in UV laser dicing the SiC wafer, and the dicing surface of good quality can be obtained only when the parameters of laser source and dicing technology vary in a narrow range. Contrarily, the SiC wafer dicing technology using high-pressure water-assisted YAG laser has a perfect flexibility with the laser source and dicing apparatus, and the good dicing surface can be obtained even if the process parameters vary in a wide range.

Thickness uniformity of an AT-cut quartz crystal wafer is essential requirement for higher productivity of quartz resonator in the sense of reducing the frequency adjusting process after dicing the wafer. However, commercially available quartz crystal wafers typically have a thickness distribution of ±0.1%, which is induced in conventional mechanical fabrication processes, such as cutting with a wire saw, lapping and polishing. Furthermore, owing to the poor parallelism and the existence of subsurface damage, many spurious peaks, which deteriorate resonance characteristics, are observed in a resonant curve. To resolve these issues, we proposed a new damage-free finishing method to correct the thickness distribution of an AT-cut quartz crystal wafer by the numerically controlled scanning of a localized atmospheric pressure plasma. By applying a new finishing process, the thickness uniformity of a commercially available AT-cut quartz crystal wafer was improved to less than 50 nm level by applying one correcting process without any subsurface damage. Furthermore, applying of the pulse-modulated-plasma drastically decreased the correcting time of the thickness distribution without breaking of the quartz crystal wafer by the thermal stress.

Nowadays, die attach film (DAF) gaining popularity in microelectronic packaging as integral part in facilitating the growth of wafer level packaging and stacked die packaging. DAF applied to the backside of wafers prior to saw have many advantages, such as the elimination of the epoxy dispensed process step and the reduction of epoxy related failure mode. However, the dicing process for DAF wafer usually associated with sidewall chipping, DAF whiskering and crack that will affect reliability of Quad Flat Non-Leaded (QFN) stacked die. Blade properties and characteristics are the crucial factor in analyzing the DAF dicing results. In this paper, we evaluate the blade characteristics before and after DAF wafer dicing process for our stacked die packaging. The qualitative measure by means of the Scanning Electron Microscope (SEM) and Energy Dispersive X-Ray (EDX) analysis were performed in order to understand the lamination and dulling effect on blade surface. The obtained results showed that sawing polymeric material such as wafer laminated with DAF induces lamination of polymeric material onto the blade surface and reduce blade cutting edge. As a result, reduce the quality of DAF dicing process.

Semiconductor devices are usually formed on a single silicon wafer during a batch processing method. Individual devices are separated from the wafer during the wafer sawing or dicing step. Subsequent packaging processes are then performed on the individual devices, whose edge portions are very susceptible to mechanical damage from the sawing process. Defects formed along device edges due to the dicing saw blade often provide potential sites for serious reliability problems. If the scribing area is reduced, the number of the separated devices from a single wafer increases, which results in productivity improvement. However, the closer the scribing position of the saw blade comes to the active device pattern, the greater possibility of sawing-induced damage to the active pattern is. Thus, this work shows methods to reduce the negative impact of the saw blade while maintaining close proximity of the scribe lines to the IC devices. In particular, this work suggests that a decrease in the size of the diamond particles embedded in the saw blade and in the rotation speed of the saw blade might contribute to the prevention of sawing-induced damage to device patterns.

Lead magnesium niobate-lead titannate single crystal (abbreviated as PMNT) was used to fabricate PMNT/polymer 1-3-2 piezoelectric composite with different volume fractions of PMNT, by dicing single crystal PMNT along mutually perpendicular two directions on the surface and then filling polymer into grooves. The piezoelectric, dielectric and electromechanical properties of the novel composite were determined. It was demonstrated that a thickness electromechanical coupling coefficient of the composites could reach as high as 0.75 and acoustic impendence decreased to 14.9 Mrayls (lower than 30 Mrayls of PMNT). The pulse-echo waveforms of the composites without backing were also measured. It showed a -6dB bandwidth of 88% at the center frequency of 0.95MHz.

In this paper, a new replication technique for 1D, 2D, and 3D microstructure was introduced, in which a master pattern was made of photo-curable epoxy using microstereolithography technology, an etching process, and a dicing process. Next, it was transferred onto an epoxy. Barrier ribs were selected as the 1D microstructure, and a rectangular pattern was selected as the 2D microstructure. A helical gear was selected as one of the real 3D microstructures for this study, and these were replicated from pure epoxy. In addition, the life span of the soft mold for using the micro replication process was evaluated.

This paper is devoted to the results of a diffusion welding technique applied to solve the problem of packaging for large area SiC Schottky diodes. To supply low defect density substrates for fabrication of 0.3 cm2 Schottky diodes TDI defect-reducing technology was used. Diodes were fabricated on CVD grown low-doped 4H-SiC single epitaxial layer without edge termination. Double layer Ni-Au and triple layer Ti-Ni-Au sputter metallization were used for Schottky contacts fabrication. Non-rectifying backside contacts were provided by Ni-Au metallization. Diodes were tested on-wafer and delivered for dicing, and packaging. To decrease the parasitic spreading resistance the thickness of initial sputter metallization was increased by diffusion welded 30 μm metal foil. Combined thick and plane metal layers make it possible to perform the clamp mode package used in power electronics. This scheme of packaging ensures current takeoff from the whole contact area and allows operating temperatures up to 600°C. The forward current-voltage characteristics measured at 75 A measured for packaged diodes yields 250 A/cm2 (70A) at 1.9 V forward voltage. Reverse recovery time for packaged diodes was in the range of 29-36 ns.

How to improve the surface quality of large-scale silicon wafer in the ultra-precision grinding process, will always be the most important issue discussed by the silicon wafer manufacturer. In this paper, the advantage of ultrasonic grinding is being explored. These advantages included small macro grinding force, grinding stress, low grinding heat, which will reduce the surface damage. Combined with relatively abrasive, a large-scale silicon wafer can be processed. Through the study, an experimental system for ultrasonic grinding of large-scale silicon wafer is designed. The working parameter is optimized and the expected result is obtained, which searches a new way for the practical implementation.