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With the scaling of process technologies into the nanometer regime, multiple-bit soft error problem becomes more serious. In order to improve the reliability and yield of SRAM, bit-interleaving architecture which integrated with error correction codes (ECC) is commonly used. However, this leads to the half select problem, which involves two aspects: the half select disturb and the additional power caused by half-selected cells. In this paper, we propose a new 10T cell to allow the bit-interleaving array while completely eliminating the half select problem, thus allowing low-power and low-voltage operation. In addition, the RSNM and WM of our proposed 10T cell are improved by 21% and nearly one times, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology. We also conduct a comparison with the conventional 6T cell about the leakage simulation results, which show 14% of leakage saving in the proposed 10T cell.

In this paper, we introduced an effective time delay model for SRAM compiler, which represents an important performance of SRAM. Our method divide the delay time into several periods, including decoder delay, word line delay, bit line delay and SA delay. The theory is useful in predicting the delay time when the SRAM size is changed. Simulations by Hsim in 65nm CMOS process proves a high accuracy.

A new 10T SRAM cell is proposed in this paper for simultaneously addressing the half select problem and improving the read/write stability. Without the half select condition, the proposed 10T cell allows efficient bit-interleaving to provide soft error rate protection and the dynamic power is also decreased significantly due to the reduction in the number of bitlines discharged and charged during the read and write operation. In the new 10T SRAM cell, one side of the cross-coupled inverters cuts off the pull up path or pull down path through adding two gated transistors according to the write ‘0’ or ‘1’ operation. It brings a great improvement for write stability without considering the half select disturb during the write operation. The simulation results indicate that the RSNM and WM of the proposed SRAM cell are enhanced by 130% and 58%, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology.

An efficient SRAM power modeling method based on two formula techniques is proposed, which contains a mathematical method called two-dimensional bilinear interpolation function and a segment analysis on the basis of MUX. This scheme allows us to reach the accurate modeling of SRAM power consumption without complicated calculation and specific circuit analysis. Hsim simulation in 65 nm CMOS process shows our proposed method error is closed to 5%.

In this paper, ring oscillator phase noise caused by power supply noise (PSN) with deterministic frequency is analyzed. Results show that phase noise caused by deterministic noise is only an impulse series. Compared with the jitter caused by PSN, the phase noise caused by PSN with deterministic frequency contributes considerably less to total phase noise performance. To verify the analysis method, a CMOS ring oscillator is designed and fabricated using SMIC 0.13 µm CMOS process. Comparisons between the analytical results and measurements prove the accuracy of the proposed method